Vertical transistor and method for forming the same

Details Vertical transistor and method for forming the same Vertical transistor and method for forming the same

2007-12-11

2011-11-08

Smith, Zandra (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S288000, C257SE29170, C257SE29118, C257SE29289

Reexamination Certificate

active

08053817

ABSTRACT:
A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions.

REFERENCES:
patent: 7078280 (2006-07-01), Chaudhry et al.
patent: 2001/0017384 (2001-08-01), Economikos et al.
patent: 2002/0177265 (2002-11-01), Skotnicki et al.
patent: 2005/0001257 (2005-01-01), Schloesser et al.
patent: 2007/0012994 (2007-01-01), Chou et al.
patent: 1385905 (2002-12-01), None
patent: 1996-7004357 (1996-08-01), None
patent: 10-0431709 (2004-05-01), None
patent: 10-0660881 (2006-12-01), None
patent: 100723527 (2007-05-01), None

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