Vertical timing signal generating circuit

Details Vertical timing signal generating circuit Vertical timing signal generating circuit

1998-08-19

2001-02-27

Harvey, David E. (Department: 2714)

Television

Synchronization

Control of picture position

C348S548000

Reexamination Certificate

active

06195130

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a vertical timing signal generating circuit and, particularly to a vertical timing signal generating circuit for generating a vertical timing signal by counting the pulses of a horizontal synchronous signal using a counter.
2. Description of the Prior Art
Recently a picture display equipment for processing input signals with digital circuits, such as a liquid crystal display equipment, has been widely used as a display device. In such liquid crystal display equipment, generally, horizontal synchronous signals and vertical synchronous signals are input, and the timing corresponding to the vertical direction is controlled by a vertical timing signal in order to display a picture on an adequate vertical position.
In order to generate the vertical timing signal, there is used a method of using a horizontal synchronous signal as a clock signal, counting the clock signal with a counter and then generating the vertical timing signal after the counting operation.
According to this method, the vertical synchronous signal supplied to the picture display equipment is used as a reset signal for starting the counting operation of the counter in order to completely synchronize the phase of the vertical timing signal generated by the counter with the phase of the video signal supplied to the picture display equipment. The vertical timing signal which is generated by counting the horizontal synchronous signals using the counter is used as signal indicating an operation timing such as the start timing or end timing of a picture in the vertical direction.
Here, the above-mentioned counter will be explained. The above-mentioned counter is hereinafter referred to as “vertical counter”. There has been hitherto broadly used a method in which the vertical counter for counting horizontal synchronous signals uses a horizontal synchronous signal or an Integral multiple of the horizontal signal as a clock signal while using a vertical synchronous signal as a reset signal for starting a counting operation.
Further, in order to stabilize the operation of the vertical counter in the case that the S/N ratio of the input signal is low or the input signal includes signals other than the original signal such as ghost signals, the clock signal is not directly supplied to the vertical counter, but supplied through a filter disposed in front of the vertical counter.
A conventional vertical timing signal generating circuit in this case will be explained with reference to FIG.
5
which is a block diagram showing the construction of the conventional vertical timing signal generating circuit
As shown in
FIG. 5
, the conventional vertical timing signal generating circuit includes filter
401
to which a horizontal synchronous signal Pb
405
is supplied, and vertical counter
403
to which a clock signal output from filter
401
and vertical synchronous signal Pc
407
are supplied and from which vertical timing signal Pd
409
is output.
As described above, the filter
401
is used for stabilizing the operation of vertical counter
403
when the S/N ratio of the input signals is low or the input signal contains the signal other than the original signal such as ghost signals. Vertical counter
403
counts the clock signal output from filter
401
and outputs vertical timing signal
409
.
Next, the timing of each signal in the conventional vertical timing signal generating circuit shown in
FIG. 5
will be explained with reference to FIG.
6
.
FIG. 6
shows a timing chart for video signal Pa
501
A (not shown in FIG.
5
), horizontal synchronous signal Pb
405
A, vertical synchronous signal Pc
407
A and vertical timing signal Pd
409
A.
FIG. 6
shows a timing chart during one vertical scanning period of vertical synchronous signal Pc
407
A.
It is now assumed, for example, that vertical timing signal Pd
409
A has a phase relationship as shown in
FIG. 6
where it is shown that vertical timing signal
409
becomes active (high) when the active area of video signal Pa
501
A ends. In
FIG. 6
, tv represents one vertical scanning period (it is also referred to as “one period”) of vertical synchronous signal Pc
407
A, and ty represents the phase difference between vertical synchronous signal Pc
407
A and vertical timing signal Pd
409
A. In this case, ty represents how many clocks are counted by vertical counter
403
.
As shown in
FIG. 6
, vertical timing signal Pd
409
A becomes active (high) after predetermined number has been counted up by vertical counter
403
which was reset by vertical synchronous signal Pc
407
A.
Next, the operation in such a case that the phase difference between the vertical synchronous signal and the video signal depends on the equipment outputting these signals will be explained. For example, this case is caused when the vertical timing signal generating circuit is connected to various personal computers.
In this case, an adjustment of the display frame position in the vertical direction is needed.
FIG. 7
is a timing chart of respective signals in this case.
FIG. 7
shows a timing chart for video signal Pa
501
B, horizontal synchronous signal Pb
405
B, vertical synchronous signal Pc
407
B and vertical timing signal Pd
409
B.
Similarly to the case of FIG.
6
.
FIG. 7
shows one vertical scanning period of the vertical synchronous signal. The phase difference between vertical synchronous signal Pc
407
B and vertical timing signal Pd
409
B in the case of
FIG. 7
is different from the case of FIG.
6
. This phase difference in each case is adjusted by varying the number of count of vertical counter
403
. Therefore, the phase difference between video signal Pa
501
A (
501
B) and vertical timing signal
409
A (
409
B) can be kept constant, even when the phase difference between video signal
501
A (
501
B) and vertical synchronous signal
407
A (
407
B) varies.
However, in the above-explained conventional vertical timing signal generating circuit. when the period of the vertical synchronous signal becomes shorter than its original period, there occurs a case where the vertical counter is reset before it completes the counting operation In this case, when the phase control is made so that the vertical timing signal is obtained by the counter just before the input vertical synchronous signal, there is a case where the vertical timing signal does not become active.
This problematic situation will be explained with reference to FIG.
8
.
FIG. 8
is a timing chart of each signal shown in FIG.
5
.
From the comparison between the timing chart shown in FIG.
8
and the timing chart shown in
FIG. 7
, it is observed that one vertical scanning period tv of vertical synchronous signal Pc
407
C of
FIG. 8
is shorter than that of
FIG. 7
by n. This shortening occurs due to the characteristic of a signal generating equipment such as a VCR, a personal computer the like to which the vertical timing signal generating circuit is connected.
When tv is shorter by n, the pulse of vertical timing signal
409
C which would originally appear at point S does not appear because vertical counter
403
is reset by vertical synchronous signal
407
C before vertical counter
403
count up horizontal synchronous signal
405
C for period ty.
Further, then the phase difference between vertical synchronous signal and video signal is varied every equipment as in the case of video signals generated by a personal computer, it is needed to adjust the display frame position in the vertical direction by varying the phase relationship between vertical synchronous signal and vertical timing signal generated by vertical counter
403
. However, when the count value to be counted by vertical counter
403
is changed in order to adjust the phase of vertical timing signal, the counting operation of vertical counter
403
may not be carried out, even when the vertical synchronous signal is supplied, and thus vertical timing signal
409
C may not be generated.
This problematic situation will be explained with reference to FIG.
9
.
FI

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