Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Patent
1987-12-11
1988-12-06
Groody, James J.
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
358150, 358153, H04N 510, H04N 508
Patent
active
047898968
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a vertical synchronizing pulse generating circuit for use in a television receiver, and more particularly, to a vertical synchronizing pulse generating circuit which is suited to be formed in an IC (integrated circuit).
THE DESCRIPTION OF THE PRIOR ART
Generally, in a television receiver, a signal having a frequency nfH, which is equal to an interger number times the frequency of the horizontal frequency fH, is formed in synchronization with the horizontal synchronizing signal. The signal with the frequency nfH is divided in accordance with the vertical synchronizing signal to obtain a signal having a vertical frequency fv, which is used in a vertical deflection circuit for effecting the vertical deflection. An example of such a circuit formed in an IC is an IC element LA7620 for use in a deflection circuit for an image and color, and is explained, for examples, in "'85 Sanyo Semi-Conductor Handbook Monosilic Bipolar Integrated Circuit" (issued on Mar. 20, 1985, at page 1,000).
FIG. 1 shows a vertical deflection circuit which is a part of the IC. In FIG. 1, a numeral 1 shows an IC part, wherein a video signal from an image detecting circuit is applied to a composite synchronizing separation circuit 3 through an input pin 2, whereby a composite synchronizing signal consisting of a horizontal and a vertical synchronizing signals, etc. are separated. Since the composite synchronizing signal is applied to a vertical synchronizing separation circuit 7 comprising an integration circuit 4, a clamping circuit 5, and a transistor 6, the collector of the transistor 6 can obtain a pulse signal synchronizing a vertical synchronizing singnal, and the pulse signal is impressed, as a reset signal, on a frequency divider 8.
In the meantime, a signal-generating circuit 9, which is impressed by a composite synchronizing signal obtained from the composite synchronizing separation circuit 3, generates a signal with a frequency 2fH which is 2 times as many as a horizontal frequency synchronizing a horizontal synchronizing signal. The generated signal is then impressed on the frequency divider 8 as a clock signal. Thus, the signal with a frequency 2fH is divided in the frequency divider 8 into 1/525 according to pulses from the vertical synchronizing separation circuit 7. An output signal with a vertical frequency fv which is obtained from the frequency divider 8 is applied to the base of an output transistor 10. As a result, an output pin 11 will produce driving pulses for driving a vertical deflection circuit 12.
Therefore, according to the circuit as shown in FIG. 1, a driving pulse for a vertical deflection can be obtained from a video signal.
However, in the circuit shown in FIG. 1, to obtain a vertical synchronizing signal, a capacitor is charged directly according to a composite synchronizing signal which has comparatively large level for a signal to be used in an IC. Therefore, the capacitor can not be incorporated in the IC, but is connected outside the IC chip. Accordingly, the integration circuit 4 and the clamping circuit 5 are connected outside the IC chip, resulting in the increase of parts and producing processes thereof. Also, a further problem arises that the number of pins increases, resulting in difficulty in arranging the circuit in an IC chip.
DISCLOSURE OF THE INVENTION
Taking the above problems into account, the present invention has been made, and is characterized by comprising a transistor for switching on/off according to an output signal from a composite synchronizing separation circuit which separates a composite synchronizing signal from a video signal; a capacitor which is charged or discharged according to the on or off switching of the transistor; a constant current generator for generating a constant current for charging the capacitor; a comparing circuit for comparing an output voltage of the capacitor with a reference voltage and for generating a iiscriminating signal by the result of the comparison; a frequency divider, which rece
REFERENCES:
patent: 4198659 (1980-04-01), Iijima et al.
patent: 4349839 (1982-09-01), McGinn
patent: 4463379 (1984-07-01), Hosoya
Arai Hiromi
Kishi Hiroyasu
Groody James J.
Parker Michael D.
Sanyo Electric Co,. Ltd.
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