Television – Synchronization – Sync separation
Reexamination Certificate
2000-01-19
2002-07-23
Miller, John (Department: 2614)
Television
Synchronization
Sync separation
C348S521000, C348S529000, C348S547000, C348S705000
Reexamination Certificate
active
06424379
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to vertical synchronization separation circuits which are used in a television (TV) receiver or the like for generating a vertical output pulse based on a complex synchronization signal extracted from an input image signal. More particularly, this invention relates to a vertical synchronization separation circuit which is capable of eliminating a curve on a TV screen by the generation of an appropriate vertical output pulse even in the case where a complex synchronization signal added to a copy guard signal is input.
BACKGROUND OF THE INVENTION
Conventionally, a double AFC (Auto Frequency Control) circuit is used to allow a horizontal synchronization signal to coincide with a TV screen output in the TV receiver.
FIG. 7
is a block diagram showing an outline structure of the double AFC circuit. A VCO (Voltage Controlled Oscillator)
101
of a double AFC circuit
100
shown in
FIG. 7
oscillates at n times the frequency of the horizontal synchronization signal SH, and this output is input into a frequency divider
102
. The frequency divider
102
divides the frequency of the output of the VCO
101
in a cycle of the horizontal synchronization signal SH, and at the same time, generates a signal required for allowing the output of the VCO
101
to coincide with the horizontal synchronization signal SH, and outputs this generated signal to a phase comparator
103
. The phase comparator
103
compares the phase of the horizontal synchronization signal SH with the phase of the output of the frequency divider
102
, and feeds back and outputs an error voltage corresponding to this phase difference in the result of this comparison to the VCO
101
. Consequently, a first feed back loop system R
1
is formed with the VCO
101
, frequency divider
102
, and phase comparator
103
. With this first feed back loop system R
1
, the oscillation frequency of the VCO
101
is locked to the horizontal synchronization signal SH in a definite phase relation. This first feed back loop system R
1
generates a horizontal output pulse and stops its operation for the period when the vertical output pulse is output.
On the other hand, the frequency divider
102
further generates a signal which is required for comparing the phase of the output from the frequency divider
102
with the phase of a fly back pulse FP output from a fly back transformer
106
, and outputs the generated signal to a phase comparator
105
. The phase comparator
105
compares the phase of the output from the frequency divider
102
with the phase of the fly back pulse FP, and outputs an error voltage corresponding to the phase difference in the result of this comparison to the horizontal output phase control circuit
104
. The horizontal output phase control circuit
104
generates a horizontal output pulse PH required for preparing the fly back pulse FP, and outputs it to a fly back transformer
106
. As described above, the fly back transformer
106
generates the fly back pulse FP, and outputs it FP to the phase comparator
105
. Consequently, a second feed back loop system R
2
is formed with these phase comparator
105
, horizontal output phase control circuit
104
, and fly back transformer
106
. This second fly back loop system R
2
allows the horizontal synchronization signal SH to coincide with the TV screen output. The fly back transformer
106
generates each kind of voltage which is synchronized with the horizontal synchronization signal SH, and also generates a voltage corresponding to the TV screen output. A part of the voltage is then flied back and output to the phase comparator
105
as a fly back pulse FP.
The horizontal synchronization signal SH which is input to this double AFC circuit
100
is output from a synchronizing separation section
110
.
FIG. 8
is a block diagram showing an outline structure of the synchronizing separation section
110
. As shown in
FIG. 8
, the synchronization separation section
110
outputs the horizontal synchronization signal SH and the vertical output pulse PV from the input image signal S
1
. The synchronization separation section
110
comprises a synchronization separation circuit
111
, a horizontal synchronization separation circuit
112
, and a vertical synchronization separation circuit
113
. The synchronization separation circuit
111
separates a complex synchronization signal SC in which the horizontal synchronization signal and the vertical synchronization signal exist together from the input image signal S
1
and outputs the complex synchronization signal SC to the horizontal synchronization separation circuit
112
and the vertical synchronization separation circuit
113
.
The horizontal synchronization separation circuit
112
outputs the horizontal synchronization signal SH, by which an equivalent pulse and a vertical synchronization signal are extracted from the complex synchronization signal SC, to the double AFC circuit
100
. On the other hand, the vertical synchronization circuit
113
separates only the vertical synchronization signal from the complex synchronization signal SC and outputs it as a vertical output pulse PV. The operation of the double AFC circuit
100
is suspended if the vertical output pulse PV is output.
FIG. 9
is a circuit diagram showing a detailed structure of the vertical synchronization circuit
113
. As shown in
FIG. 9
, this vertical synchronization separation circuit
113
has a first comparator
11
in which transistors TR
1
and TR
2
are operated as a differential pair. The first comparator
11
compares the complex synchronization signal SC input from an input terminal T
1
with the first reference voltage V
1
. The input terminal T
1
is connected to the base of the transistor TR
1
while the positive side of the first reference voltage V
1
is connected to the base of the transistor TR
2
. The power source
1
and the capacitor C
1
are connected to a terminal T
11
on the collector side of the transistor TR
2
. The other end of the capacitor C
1
is grounded. The other end of the current source
1
and the collector of the transistor TR
1
are connected to the power source Vcc. The emitters of the transistors TR
1
and TR
2
are connected commonly with the power source
3
, and grounded. Furthermore, the value of the current I
3
which the current source
3
outputs is set to a value larger than the current I
1
which the current source
1
outputs.
Consequently, when the first reference voltage V
1
is larger than the voltage of the complex synchronization signal SC, an electric load accumulated in the capacitor C
1
is discharged because current I
3
is larger than current I
1
. When the first reference voltage V
1
is lower than the voltage of the complex synchronization signal SC, the capacitor C
1
is charged with the current I
1
supplied by the current source
1
. Therefore, the voltage Vc that is obtained by the integration of the complex synchronization signal SC is generated in the capacitor C
1
.
The voltage Vc of this capacitor C
1
is applied to the base of the transistor TR
3
out of the transistors TR
3
and TR
4
as differential pairs which constitute the second comparator
12
. Furthermore, the second reference voltage V
2
is applied to the base of the transistor TR
4
, and the second comparator
12
compares the voltage Vc and the second reference voltage V
2
. The collector of the transistor TR
3
is connected to the power source Vcc, and the collector of the transistor TR
4
is connected to the power source Vcc via a resistor R
1
. From a connection between the collector of the transistor TR
4
and the resistor R
1
, a vertical output pulse PV is output as a comparison result. Furthermore, the emitters of the transistor TR
3
and TR
4
are connected commonly with the current source
4
, and grounded. Operation of the vertical synchronization separation circuit
113
will be explained by referring to a timing chart shown in
FIG. 10A
to FIG.
10
C.
FIG. 10A
shows a relation between the complex synchronization signal SC input to the input t
Desir Jean W.
Leydig , Voit & Mayer, Ltd.
Miller John
Mitsubishi Denki & Kabushiki Kaisha
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