Vertical synchronization processing circuit

Details Vertical synchronization processing circuit Vertical synchronization processing circuit

1992-05-27

1994-03-01

Kostak, Victor R.

Television

Synchronization

Automatic phase or frequency control

348533, H04N 504

Patent

active

052912876

ABSTRACT:
A vertical synchronization processing circuit includes a counter for counting a clock signal synchronized with a horizontal sync. signal, a circuit for resetting the counter in response to a vertical synchronization signal within a predetermined limit prohibiting reset due to a non-standard signal, a memory for storing the data counted at the timing of reset, and a circuit for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from the memory. A circuit for discriminating an existence of a vertical synchronization interval can also be provided along with a second resetting circuit for resetting the counter if the discriminating circuit detects the existence of the vertical synchronization interval when the counter counts a predetermined number of clock signals in case there is not a vertical synchronization pulse within the predetermined limit.

REFERENCES:
patent: 4025951 (1977-05-01), Eckenbrecht
patent: 4228461 (1980-10-01), Weissmuller
patent: 4231064 (1980-10-01), Uchida
patent: 4556905 (1985-12-01), Ikejiri
patent: 4843469 (1989-06-01), Boyce
Patent Abstracts of Japan, vol. 10, No. 359, Dec. 3, 1986 (Mitsushige).

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