Vertical synchronization circuit for television receivers

Details Vertical synchronization circuit for television receivers Vertical synchronization circuit for television receivers

1979-06-13

1980-12-09

Griffin, Robert L.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

H04N 510

Patent

active

042387698

ABSTRACT:
An improved vertical synchronization system for a television receiver provides both good noise immunity and improved interlace. This is achieved by employing two parallel vertical synchronization circuits between the synchronizing signal input of the vertical oscillator and synchronizing signal source. One of these vertical synchronizing circuit paths comprises a standard integrator circuit adjusted for optimum noise immunity and the other is a cascaded digital circuit adjusted for improved interlace but having poorer noise immunity than the first circuit. The digital circuit produces a synchronizing pulse slightly ahead of the pulse produced by the conventional circuit so that the digital circuit normally controls the operation of the oscillator. Whenever extreme noise conditions exist, the digital circuit is disabled and the conventional synchronizing signal circuit takes over the synchronizing task.

REFERENCES:
patent: 2543015 (1951-02-01), Grieg
patent: 2763718 (1956-09-01), Collins
patent: 3074027 (1963-01-01), Rout
patent: 3487167 (1969-12-01), Riggin
patent: 3532810 (1970-10-01), Steinberg
patent: 3619497 (1971-11-01), Ellis
patent: 3751588 (1973-08-01), Eckenbrecht
patent: 3809809 (1974-05-01), Vidovic
patent: 4001715 (1977-01-01), Fukaya

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