Vertical semiconductor integrated circuit chip packaging

Details Vertical semiconductor integrated circuit chip packaging Vertical semiconductor integrated circuit chip packaging

1980-11-28

1984-01-17

Hecker, Stuart N.

Static information storage and retrieval

Hardware for storage elements

361398, 365 72, G11C 504

Patent

active

044266898

ABSTRACT:
A semiconductor chip is so designed that the signal and power terminals are brought to one edge of the integrated circuit chip. The integrated circuit chip is then mounted vertically on a substrate which provides signal interconnection and power distribution to the integrated circuit chips as well as a thermal path for conducting heat away from the chips. The electrical connection from the semiconductor chip to the substrate may be by solder reflow or thermal compression bonding techniques. The package is particularly advantageous for memory integrated circuit chips. The vertical integrated circuit chips may alternatively be carried by a tape carrier which is formed into a convoluted form with all integrated circuit chips positioned substantially vertically thereon. This carrier is then bonded electrically and physically to a substrate in areas associated with the integrated circuit chips so that when the substrate is substantially horizontal the integrated circuit chips are substantially vertical in relation thereto. In this alternative, electrical connections may be made to more than one edges of the integrated circuit chips.

REFERENCES:
patent: 3065383 (1962-11-01), Guillemot
patent: 3341742 (1967-09-01), Klehm
patent: 3469953 (1969-09-01), St. Clair et al.
patent: 3766439 (1973-10-01), Isaacson
patent: 3873889 (1975-03-01), Leyba
patent: 4059849 (1977-11-01), Mitchell
Doo et al., "High Performance Package for Memory", IBM Tech. Disc. Bul., vol. 21, No. 2, 7/78, pp. 585-586.

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