Vertical semiconductor integrated circuit chip packaging

Details Vertical semiconductor integrated circuit chip packaging Vertical semiconductor integrated circuit chip packaging

1979-03-12

1981-05-05

Hecker, Stuart N.

Static information storage and retrieval

Hardware for storage elements

365 72, G11C 504, G11C 506

Patent

active

042662826

ABSTRACT:
A semiconductor chip is so designed that the signal and power terminals are brought to one edge of the integrated circuit chip. The integrated circuit chip is then mounted vertically on a substrate which provides signal interconnection and power distribution to the integrated circuit chips as well as a thermal path for conducting heat away from the chips. The electrical connection from the semiconductor chip to the substrate may be by solder reflow or thermal compression bonding techniques. The package is particularly advantageous for memory integrated circuit chips. The vertical integrated circuit chips may alternatively be carried by a tape carrier which is formed into a convoluted form with all integrated circuit chips positioned substantially vertically thereon. This carrier is then bonded electrically and physically to a substrate in areas associated with the integrated circuit chips so that when the substrate is substantially horizontal the integrated circuit chips are substantially vertical in relation thereto. In this alternative, electrical connections may be made to more than one edges of the integrated circuit chips.

REFERENCES:
patent: 3447037 (1969-05-01), Nissim
patent: 3702464 (1972-11-01), Castrucci
patent: 3898631 (1975-08-01), Brown et al.
patent: 3916266 (1975-10-01), Bennett et al.
patent: 3949274 (1976-04-01), Anacker
patent: 4050061 (1977-09-01), Kitagawa
patent: 4156938 (1979-05-01), Proebsting et al.
Agusta, High-Density Packaging of Monolithic Circuits, IBM Tech. Disc. Bul., vol. 10, No. 7, 12/67, pp. 890-891.
Kryzaniwsky, Chip Air Cooling Arrangement, IBM Tech. Disc. Bul., vol. 14, No. 10, 3/72, p. 2911.

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