Vertical probe housing

Details Vertical probe housing Vertical probe housing

1999-04-30

2001-03-06

Sircus, Brian (Department: 2839)

Electrical connectors

Including handle or distinct manipulating means

Randomly manipulated implement

C439S066000

Reexamination Certificate

active

06196866

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a test probe housing for contacting rows of densely spaced bonding pads such as memory devices on a wafer.
BACKGROUND OF THE INVENTION
Vertical probes are typically used to make electrical contact between the chip pads of chips carried on wafers and a testing system or machine used for device testing. The device chip pads are densely spaced, and the function of the vertical probe is to “fan-out” or enlarge this dense spacing to accommodate the larger spacing between adjacent electrical connectors found in most testing equipment.
A typical vertical probe is the cobra probe described in U.S. Pat. No. 4,027,935. This probe consists of upper and lower dies, a housing supporting the two dies, and multiple contacts formed from thin wire, e.g. 4 to 5 mils in diameter. The contacts are generally sharpened to a fine point, like a pencil point, for improving the ability of the probe tip to penetrate aluminum oxide on the chip pads. In addition, the contacts are mounted in the dies in a manner such that minor differences in the topography of different chip pads are accommodated by the inherent resiliency of the contacts.
SUMMARY OF THE INVENTION
The present invention is directed to an improvement over known vertical probes wherein the die/housing assembly forming the basic structure for supporting the contacts is replaced by a single, unitary body. With this structure, the inventive vertical probe is easier to manufacture than vertical probes of current design. Moreover, repair of the inventive vertical probe is also easier, since the basic structure of the probe need not be disassembled to achieve access to the device interior for replacing broken contacts.
Thus, the present invention provides an improved vertical probe for use in testing multiple chips carried on a wafer comprising a unibody of dielectric material having a testing surface and an output surface spaced from the testing surface. The body includes at least one chamber defining an opening in the output surface, the rim of the opening being formed by a lip of the dielectric material. The device also includes a testing wall between the testing surface and the chamber. Multiple contacts, each having a distal end with a tip for contacting one of the pads, are received in the respective holes in the testing wall. Each contact has an output end opposite the distal end.
The invention also deals with means for providing ready access to the interior of the probe to facilitate the loading of contacts and also the removal and replacement of faulty contacts. More specifically, the invention comprises a probe for probing a plurality of chip pads. The probe comprises a contact and a first die, the die having a first surface containing a first hole with a contact extending at least part way through the first hole. An opening in the surface in proximity to the first hole accesses a chamber within the probe thereby permitting the contact to be loaded into the first hole. Typically, the first die is an upper die of a probe useful for vertical probing. The probe also includes a lower die comprising a surface containing a second hole offset from the first hole. The contact slidably extends through the second hole and provides a spring force for contacting a substrate, e.g. a chip pad, facing the second hole. The probe may comprise a plurality of contacts arranged to test a plurality of chips. The first and second dies can be fabricated from a single piece of material or can be produced from separate subcomponents which are then assembled with a midplate into the probe body. The probe further comprises a dielectric film adjacent the contact to prevent shorting and to facilitate sliding of the distal end of the contact in the second hole. The dielectric film preferably comprises a polyimide film having a thickness between about 2 mils and 5 mils. The opening through the first die preferably is sized to accommodate one or more decoupling capacitors.


REFERENCES:
patent: 3806801 (1974-04-01), Bove
patent: 4027935 (1977-06-01), Byrnes et al.
patent: 4523144 (1985-06-01), Okubo et al.
patent: 5320559 (1994-06-01), Uratsuji et al.
patent: 5399982 (1995-03-01), Driller et al.
patent: 5670889 (1997-09-01), Okubo et al.
patent: 1406829 (1988-06-01), None
“Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's” by Y. Nakagome, IEEE Journal of Solid State Circuits, vol. 28, No. 4 (Apr., 1993).

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