Vertical power JFET with low on-resistance for high voltage...

Details Vertical power JFET with low on-resistance for high voltage... Vertical power JFET with low on-resistance for high voltage...

2007-06-26

2007-06-26

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S213000, C257SE29242

Reexamination Certificate

active

10828773

ABSTRACT:
A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P− region is disposed under the P+ region. The P− region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P− region may be disposed adjacent to a first portion of the P+ region while another P− region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.

REFERENCES:
patent: 5597765 (1997-01-01), Yilmaz et al.
patent: 5702987 (1997-12-01), Chen et al.
patent: 6551865 (2003-04-01), Kumar et al.
patent: 6774417 (2004-08-01), Lin et al.
patent: 6841812 (2005-01-01), Zhao
patent: 6855970 (2005-02-01), Hatakayama et al.

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