Patent
1987-05-12
1988-11-22
Edlow, Martin H.
357 55, 357 41, 357 59, H01L 2978, H01L 2906, H01L 2702, H01L 2904
Patent
active
047869534
ABSTRACT:
A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.
REFERENCES:
patent: 4206005 (1980-06-01), Yeh et al.
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4663644 (1987-05-01), Shimizu
Minegishi Kazushige
Miura Kenji
Morie Takashi
Nakajima Shigeru
Somatani Toshifumi
Edlow Martin H.
Limanek Robert P.
Nippon Telegraph & Telephone
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