Vertical MOS-FET devices having a planar multicell structure

Details Vertical MOS-FET devices having a planar multicell structure Vertical MOS-FET devices having a planar multicell structure

1983-12-05

1986-12-02

Edlow, Martin H.

357 41, H01L 2910

Patent

active

046268804

ABSTRACT:
A vertical MOS-FET device having a planar multicell structure which is constituted by an assembly of elementary cells of a polygonal form having a source zone, a shortcircuit region, a channel zone and a drain zone. In the space between adjoining apices of a number of elementary cells there are provided complementary elements having a construction similar to that of the previously-mentioned cells but having a polygonal form adapted to the configuration of the cells. Thus, the overall length of the channel zones per unit surface area can be optimized.

REFERENCES:
patent: 4072975 (1978-02-01), Ishitani
patent: 4148047 (1979-04-01), Hendrickson
patent: 4345265 (1982-08-01), Blanchard
Tihanyi, "Functional Integration of Power MOS and Bipolar Devices", Electron Devi., 1980 IEEE, pp. 75-78.
Design News, "High-Powered P-Channel M.O.S. F.E.T.S.", Electronic Product Design, Oct. 1980, p. 10.
Tarng, "On-Resistance Characterization of VDMOS Power Transistors", IEDM 81, pp. 429-431.

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