Vertical mask for defining a region on a wall of a semiconductor

Details Vertical mask for defining a region on a wall of a semiconductor Vertical mask for defining a region on a wall of a semiconductor

1997-02-24

1998-06-02

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Groove

257798, H01L 2906

Patent

active

057604614

ABSTRACT:
A device and method are described for defining a region on a wall of a semiconductor structure, such as a sidewall of a trench formed in a semiconductor substrate. The method includes the steps of forming a vertical structure above the semiconductor structure and spaced parallel to the wall; providing within the vertical structure an area of one of transparence, reflection or refraction; and projecting light at a given angle to the wall, wherein only a portion of the light passes the vertical structure via the area provided therein to impinge upon the wall of the semiconductor structure, and thereby define the region on the wall. As an alternative, the area can comprise an aperture in the vertical structure such that the vertical structure can be employed as a mask to direct selective ion implantation of the wall.

REFERENCES:
patent: 3908262 (1975-09-01), Stein
patent: 4415371 (1983-11-01), Soclof
patent: 4466178 (1984-08-01), Soclof
patent: 4549927 (1985-10-01), Goth et al.
patent: 4751458 (1988-06-01), Elward, Jr.
patent: 4918027 (1990-04-01), Fuse et al.
patent: 5047359 (1991-09-01), Nagatomo
patent: 5096849 (1992-03-01), Beilstein, Jr. et al.
patent: 5101261 (1992-03-01), Maeda
patent: 5147823 (1992-09-01), Ishibashi et al.
patent: 5306390 (1994-04-01), Peek
patent: 5376225 (1994-12-01), Wakabayashi et al.
patent: 5391506 (1995-02-01), Tada et al.
patent: 5547883 (1996-08-01), Kim
patent: 5578508 (1996-11-01), Baba et al.
Soychak et al., "Technique To Selectively Dope Semiconductor Trench Walls and Bottom," IBM Technical Disclosure Bulletin, vol. 30, No. 8, pp. 268-269, Jan. 1988.
Cronin et al., "Line and Via Intrerconnect Structure Using A Single Mask," IBM Technical Disclosure Bulletin, vol. 32, No. 12, pp. 146-147, May 1990.

Affiliated with

Also associated with

Rating

Vertical mask for defining a region on a wall of a semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical mask for defining a region on a wall of a semiconductor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical mask for defining a region on a wall of a semiconductor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1463099