Vertical inverter circuit

Details Vertical inverter circuit Vertical inverter circuit

1988-04-22

1989-03-07

Edlow, Martin H.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307445, 307304, 307450, 357 42, 357 234, H03K 19017, H03K 19094, H01L 2702

Patent

active

048109061

ABSTRACT:
One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N- layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

REFERENCES:
patent: 3518509 (1970-06-01), Cullis
patent: 4028556 (1977-06-01), Cachier et al.
patent: 4038563 (1977-07-01), Zuleeg et al.
patent: 4462040 (1984-07-01), Ho et al.
patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 4566025 (1986-01-01), Jastrzebski et al.

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