Vertical interconnect process for silicon segments with...

Details Vertical interconnect process for silicon segments with... Vertical interconnect process for silicon segments with...

1997-08-21

2001-07-03

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S723000, C257S717000

Reexamination Certificate

active

06255726

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for stacking and interconnecting segments of silicon, and more particularly to an apparatus for stacking segments, which include a plurality of die and beveled edge walls, and interconnecting the segments on the edges of the stack using electrically conductive epoxy.
For many years, electrical components such as transistors and integrated circuits have been made using wafers of semiconductor material, including silicon and germanium. Integrated circuits have been provided on the wafer using various techniques known as etching, doping, and layering. Individual integrated circuits that are provided on the wafer are referred to as die, and include contact points called bond pads for external electrical connections. Typically, the die on the wafer are separated from one another by cutting the wafer along boundaries defining the die. Once the die are cut from the wafer, they are referred to as chips, and are packaged for use. In recent years, the proliferation of more powerful electronic systems has led to an increased need for higher density integrated circuit packages.
One method for creating higher density packages attempts to create entire computer systems on a single wafer using wafer scale integration (WSI) techniques. WSI technology attempts to laterally wire together all the die on a wafer using wires to interconnect the die. However, in order to create the necessary interconnections between the die, many wires are required that are extremely thin and difficult to create.
A second method for creating higher density packages attempts to reduce the area required for placing the chips on a circuit board by physically stacking the chips vertically. One chip stacking technique mounts individual die on ceramic carriers, encapsulates both the die and the carrier, stacks the carriers, and then mounts the stack on a printed circuit board. In this technique, all the die in the stack are interconnected by connecting the leads of the die to the printed circuit board via metal pins. This method results in an unusually high pin count on the circuit board which reduces the reliability of the circuitry because the high pin count increases the possibility that one of the many pins may become disconnected from the board.
Another chip stacking method uses a more complex process to stack die, as disclosed in U.S. Pat. No. 5,104,820 issued Apr. 14, 1992. As shown in
FIG. 1
, this method modifies individual chips
10
so that they may be stacked by adding a pattern of metallization, called rerouting leads
12
, to the surface of the wafer. The rerouting leads
12
extend from the bond pads
14
on the chip
10
to newly formed bond pads
11
, and are arranged so that all the rerouting leads
12
terminate on one side of the modified chip
10
. Each modified chip
10
is then cut from the wafer, as shown by the dotted lines, and assembled into a stack (not shown). The stack is assembled in a manner such that all the leads
12
of the modified chips
10
are aligned along the same side of the stack. The side of the stack having the leads
12
is then etched and polished so that a cross section of the leads
12
on each of the modified chips
12
is accessible. After the leads
12
are exposed, a layer of metallization is applied to the leads
12
along the side of the stack in order to electrically connect each of the modified chips
10
in the stack. The stack is then mounted and connected to a substrate which in turn is connected to conventional circuitry.
The method of rerouting leads offers improvement in circuit density over prior methods but is complex and expensive. In addition, as shown in
FIG. 1
, the rerouting leads
12
extend over five adjacent die
15
through
19
, which are destroyed when the modified chip
10
is cut out of the wafer. In this method, five die are sacrificed for every chip
10
that is modified.
Another method for creating higher density circuits creates stacks from entire wafers, rather than individual chips, to form a wafer array. In some devices, the wafers in the stack are electrically interconnected using solid vertical columns of metallic conductive feed-throughs, such as copper. The use of solid feed-throughs to interconnect wafers may cause damage to the array due to differential thermal coefficients of expansion during thermal cycles. Furthermore, the process is costly and makes the wafers difficult to separate for repairs.
Other methods also exist to interconnect stacks of wafers, as disclosed in, for example, U.S. Pat. No. 4,897,708 issued Jun. 30, 1990, and U.S. Pat. No. 4,954,875 issued Sep. 4, 1990. These methods provide each wafer in the stack with coned-shaped through holes which expose bonding pads on the wafers. The bond pads of the wafers in the stack are then electrically connected by either filling the through holes with electrically conductive liquid, or inserting an electrically conductive compliant material into the through holes, to provide a continuous vertical electrical connection between the wafers. While avoiding the disadvantages of using solid vertical columns of metal to interconnect wafers, the use of electrically conductive liquids and conductive materials requires special tooling to fill the through holes. Furthermore, for some applications, it may not be desirable to use stacks of entire wafers due to size constraints of the electrical device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved apparatus for stacking and interconnecting segments of silicon.
In one preferred embodiment, the present invention provides an apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments.
After the segments are cut from the wafer, the segments are placed on top of one another to form a stack, as distinguished from both a stack of individual chips and a stack of entire wafers. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy filaments or lines to one or more sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provides a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. The stack of electrically interconnected segments is then mounted above, on or below the surface of a circuit board and electrically connected to circuits on the board by applying traces of electrically conductive epoxy between the bonding pads on the top segment of the stack and the circuit board.
According to a further aspect of the present invention, an insulating dielectric process is used to electrically isolate the entire edge of the die. The dielectric isolation process provides a conformal isolation coating around the edge of the die to protect and insulate the die.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.


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