Vertical integrated package apparatus and method

Details Vertical integrated package apparatus and method Vertical integrated package apparatus and method

2006-06-27

2006-06-27

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S457000, C438S458000, C438S459000

Reexamination Certificate

active

07067352

ABSTRACT:
A method of fabricating integrated circuits from a plurality of semiconductor dice, each semiconductor die defining a top side and a bottom side, includes the steps of attaching the bottom sides of the plurality of semiconductor dice to a substrate so that the plurality of semiconductor dice are in adjacent disposition and define one or more bending regions; creating a thin film interconnect on the top sides of the plurality of semiconductor dice and over one or more die gap regions so that the plurality of semiconductor dice are electrically interconnected; removing the substrate from the bottom sides of the plurality of semiconductor dice; and bending the thin film interconnect at the one or more die gap regions so that the bottom sides and the top sides of the semiconductor dice overlap to form a stacked plurality of semiconductor dice.

REFERENCES:
patent: 4783695 (1988-11-01), Eichelberger
patent: 5345205 (1994-09-01), Kornrumpf
patent: 5448511 (1995-09-01), Paurus et al.
patent: 5452182 (1995-09-01), Eichelberger et al.
patent: 5776797 (1998-07-01), Nicewarner et al.
patent: 6699730 (2004-03-01), Kim

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