Vertical insulated gate transistor and method of manufacture

Details Vertical insulated gate transistor and method of manufacture Vertical insulated gate transistor and method of manufacture

1994-08-31

1995-12-05

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257263, 257284, 257330, 257333, 257341, 257622, 437 40, 437107, 437133, 437703, 437228, 437913, H01L 29161, H01L 21265

Patent

active

054731763

ABSTRACT:
A vertical insulated gate transistor such as a UMOSFET is manufactured. A source region of first conductivity type is formed on the bottom surface of a substrate. A base region of second conductivity type is formed on the source region. A low-impurity-concentration drift region is formed on the base region. On the top surface of this multilayer structure, a truncated U groove is formed. A buried gate electrode is formed inside the truncated U groove. This structure is effective to reduce gate-drain capacitance Cgd, gate-source capacitance Cgs, and drain resistance r.sub.d, thereby realizing a high-frequency high-output device. A distance between the gate and the drain is determined in a self-aligning manner, so that a fine structure and a high-frequency operation are easily realized and production yield is improved.

REFERENCES:
patent: 5298780 (1994-03-01), Harada

Affiliated with

Also associated with

Rating

Vertical insulated gate transistor and method of manufacture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical insulated gate transistor and method of manufacture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical insulated gate transistor and method of manufacture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1375689