Vertical fuse and method of fabrication

Details Vertical fuse and method of fabrication Vertical fuse and method of fabrication

1979-10-04

1982-01-19

Fears, Terrell W.

Static information storage and retrieval

Read only systems

Semiconductive

365105, 365175, G11C 1140

Patent

active

043120466

ABSTRACT:
In a memory array wherein each cell includes an emitter follower, a diode is formed on the emitter by a thin layer which is capable of being shorted by vertical migration of bit line atoms through the layer and into the emitter region. The thin layer is fabricated by epitaxially growing the thin layer over the wafer with the emitter diffusion aperture open, oxidizing the epitaxial layer, selectively removing portions of the polycrystalline epitaxial layer and removing the oxide from the remaining epitaxial layer in the emitter diffusion aperture.

REFERENCES:
patent: 4208727 (1980-06-01), Redwine

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