Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2007-06-12
2007-06-12
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S003000, C257S288000, C257S377000, C257S382000, C257S383000, C257S384000, C257S388000, C257S412000
Reexamination Certificate
active
11135227
ABSTRACT:
A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.
REFERENCES:
patent: 6897098 (2005-05-01), Hareland et al.
patent: 2003/0211724 (2003-11-01), Haase
patent: 2005/0064185 (2005-03-01), Buretea et al.
patent: 2005/0167655 (2005-08-01), Furukawa et al.
Chi, et al., “High Performance Silicon Nanowire Field Effect Transistors”, Nano Letters, 2003, vol. 3, No. 2, 2003 American Chemical Society, Published on Web Jan. 1, 2003, pp. 149-152.
Greytak, et al., “Growth and transport properties of complementary germanium nanowire field-effect transistors”, Applied Physics Letters, vol. 84, No. 21, May 24, 2004, pp. 4176-4178.
Ng, et al., “Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor”, Nano Letters, vol. 4, No. 7, 2004 American Chemical Society, Published on Web May 29, 2004; pp. 1247-1252.
Duan, et al., “High-performance thin-film transistors using semiconductor nanowires and nanoribbons”, Nature, vol. 425, Sep. 18, 2003, pp. 274-278.
Yang, et al., “25-nm p-Channel Vertical MOSFET's with SiGeC Source Drains”, IEEE Electron Device Letters, vol. 20, No. 6, Jun. 1999, pp. 301-303.
Hergenrother, et al., “The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length”, IEEE, 1999.
Tung, et al., “Growth of Single crystal epitaxial silicides on silicon by the use of template layers”, 1983 American Institute of Physics, Appl. Phys. Lett. 42 (10), May 15, 1983, downloaded Mar. 28, 2005 to 129.34.20.23, pp. 888-890.
Tung, et al., “Formation of Ultrathin Single-Crystal Silicide Films on Si: Surface and Interfacial Stabilization of Si-NiSi2 Epitaxial Structures”, Physical Review Letters, vol. 50, No. 6, Feb. 7, 1983, pp. 429-432.
Cohen Guy Moshe
Solomon Paul M.
International Business Machines - Corporation
Scully , Scott, Murphy & Presser, P.C.
Soward Ida M.
Tuchman, Esq. Ido
LandOfFree
Vertical FET with nanowire channels and a silicided bottom... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertical FET with nanowire channels and a silicided bottom..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical FET with nanowire channels and a silicided bottom... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3854129