Vertical-etch direct moat isolation process

Details Vertical-etch direct moat isolation process Vertical-etch direct moat isolation process

1982-03-02

1983-11-29

Hoffman, James R.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427 39, 427 451, 427 99, H01L 2700

Patent

active

044180942

ABSTRACT:
Direct Moat Isolation for VLSI integrated circuit structures is formed by growing oxide over the entire substrate area, and then cutting windows in the oxide, using an anisotropic polymer-free oxide etch, where moat regions are to be formed. To prevent polysilicon filamentation, gate patterning is performed with an extremely selective polysilicon etch. The combination of these processing steps permits a direct moat isolation device fabrication process which is insensitive to the oxide sidewall angle, increasing yield and permitting extremely compact isolation structures to be formed.

REFERENCES:
Parrillo et al., "Twin-Tub CMOS-A Technology for VLSI Circuits", 1980 IEDM, Paper No. 29.1.
Kahng et al., "A Method for Area Saving Planar Isolation Oxides Wing Oxidation Protected Sidewalls", J. Electrochem. Soc.: Solid State Sci. & Tech., vol. 127, pp. 2468-2471, (1980).
Kurosawa et al., "A New Buried-Oxide Field Isolation for VSLI Devices", 1981 Device Research Conference.

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