Vertical Enhancement-mode Group III-V compound MISFETs

Details Vertical Enhancement-mode Group III-V compound MISFETs Vertical Enhancement-mode Group III-V compound MISFETs

1986-08-15

1988-07-05

James, Andrew J.

357 234, 357 55, H01L 2978

Patent

active

047558679

ABSTRACT:
A vertical, enhancement mode InP MISFET includes a conducting n-type substrate, a semi-insulating Fe-doped InP blocking layer on the substrate, a conducting layer formed in the blocking layer, a groove which extends through both the conducting layer and the blocking layer, a borosilicate dielectric layer formed on the walls of the groove, a gate electrode formed on the dielectric layer, drain electrodes formed on each side of the gate electrode, and a source electrode formed on the bottom of the substrate. When a positive gate voltage relative to the source is applied, conduction channels are formed along the sidewalls of the groove, and current flows vertically from drain to source.

REFERENCES:
patent: 4568958 (1986-02-01), Baliga
"Channel Mobility Enhancement in InP Metal-Insulator-Semiconductor Field-Effect Transistors", Applied Physics Letters, vol. 46, No. 4, 1985, pp. 416-418, K. P. Pande.
"X-Band Self-Aligned Gate Enhancement-Mode InP MISFETs", Electron Device, vol. ED-30, 1983, pp. 811-815, T. Itoh, et al.
"High-Power InP MISFETs", Electron Letters, vol. 19, No. 12, 1983, pp. 433-434, M. Armand, et al.
"Monolithically Integrated In.sub.0.53 Ga.sub.0.47 AS-PIN/InP-MISFET Photo-Receiver", Electron Letters, vol. 20, 1984, pp. 314-315, K. Kasahara, et al.
"Growth of Fe-Doped Semi-Insulating InP by MOCVD", Journal of Crystal Growth, vol. 69, 1984, pp. 10-14, J. A. Long, et al.
"The Effect of Gas Temperature on the Growth of InP by Atmospheric Pressure Metal-Organic Chemical Vapor Deposition Using Trimethyl Indium and PH.sub.3 Sources", Journal of Electronic Materials, vol. 14, 1985, pp. 563-572, J. L. Zilko, et al.

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