Active solid-state devices (e.g. – transistors – solid-state diode – Bulk effect device – Bulk effect switching in amorphous material
Reexamination Certificate
2006-05-23
2006-05-23
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Bulk effect device
Bulk effect switching in amorphous material
C257S200000
Reexamination Certificate
active
07049623
ABSTRACT:
A vertical elevated pore structure for a phase change memory may include a pore with a lower electrode beneath the pore contacting the phase change material in the pore. The lower electrode may be made up of a higher resistivity lower electrode and a lower resistivity lower electrode underneath the higher resistivity lower electrode. As a result, more uniform heating of the phase change material may be achieved in some embodiments and better contact may be made in some cases.
REFERENCES:
patent: 5414271 (1995-05-01), Ovshinsky et al.
patent: 5789758 (1998-08-01), Reinberg
patent: 5920788 (1999-07-01), Reinberg
patent: 6284643 (2001-09-01), Reinberg
patent: 6339544 (2002-01-01), Chiang et al.
patent: 6507061 (2003-01-01), Hudgens et al.
patent: 6545287 (2003-04-01), Chiang
patent: 6566700 (2003-05-01), Xu
patent: 6586761 (2003-07-01), Lowrey
patent: 6791102 (2004-09-01), Johnson et al.
patent: 2002/0093100 (2002-07-01), Gonzalez et al.
patent: WO 00/57498 (2000-09-01), None
Hwang, Y.N., Hong, J.S., Lee, S.H., Ahn, S.J., Jeong, G.T., Koh, G.H., Kim, H.J., Jeong, W.C., Lee, S.Y., Park, J.H., Ryoo, K.C.., Horii, H., Ha, Y.H., Yi, J.H., Cho, W.Y., Kim, Y.T., Lee, K.H., Joo, S.H., Park, S.O., Jeong, U.I., Jeong, H.S. and Kim, Kinam, “Completely CMOS-Compatible Phase-Change Nonvolatile RAM Using NMOS Cell Transistors,” presented at 2003 19thIEEE Non-Volatile Semiconductor Memory Workshop, Monterey, California, Feb. 26-20, 2003.
Ha, Y.H., Yi, J.H., Horii, H., Park, J.H., Joo, S.H., Park, S.O., Chung, U-In and Moon, J.T., “An Edge Contact Type Cell for Phase Change RAM Featuring Very Low Power Consumption,” presented at IEEE 2003 Symposium on VLSI Technology, Kyoto, Japan, Jun. 12-14, 2003.
Hwang, Y.N., Hong, J.S., Lee, S.H., Ahn, S.J., Jeong, G.T., Koh, G.H., Oh, J.H., Kim, H.J., Jeong, W.C., Lee, S.Y., Park, J.H., Ryoo, K.C., Horii, H., Ha, Y.H., Yi, J.H., Cho, W.Y., Kim, Y.T., Lee, K.H., Joo, S.H., Park, S.O., Chung, U.I., Jeong, H.S. and Kim, Kinam, “Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24 mm-CMOS Technologies,” presented at IEEE 2003 Symposium on VLSI Technology, Kyoto, Japan, Jun. 12-14, 2003.
Horii, H., Yi, J.H., Park, J.H., Ha, Y.H., Baek, I.G., Park, S.O., Hwang, Y.N., Lee, S.H., Kim, Y.T., Lee, K.H., Chung, U-In and Moon, J.T., “A Novel Cell Technology Using N-doped GeSbTe Films for Phase Change RAM,” presented at IEEE 2003 Symposium on VLSI Technology, Kyoto, Japan, Jun. 12-14, 2003.
Nhu David
Ovonyx Inc.
Trop Pruner & Hu P.C.
LandOfFree
Vertical elevated pore phase change memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertical elevated pore phase change memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical elevated pore phase change memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3554076