Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Patent
1995-12-22
1996-11-12
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
257 49, 257327, 257328, 257329, 257335, 257336, 257344, 257377, 257412, 257618, 437 40, 437 43, 437 46, 437109, 437191, 437233, 437235, H01L 2976, H01L 21265
Patent
active
055742947
ABSTRACT:
A process for making a dual gated thin film transistor (TFT), having a sidewall channel and self-aligned gates and off-set drain is disclosed. A substrate having a top surface with insulating regions is provided. A bilayer having a polysilicon bottom layer and an insulating top layer, is patterned to form the bottom electrode of the TFT with an insulating layer over it. A first gate insulator is formed in contact with sides of the bottom electrode. A layer of second polysilicon having two end source and drain regions and a middle channel region is formed with the channel region being vertical along the side of the bottom electrode and overlying insulator layer and in contact with the first gate insulator. A second gate insulator is formed on the second polysilicon. A contact opening is etched in the insulating layers overlying the bottom electrode, in a region away from the second polysilicon to expose surface of part of the bottom electrode. A third polysilicon layer is deposited and patterned to have a horizontal region overlapping the contact opening to make contact to the bottom electrode, and to have sidewall electrode regions in contact with the second gate insulator and superadjacent to the channel region act as the top electrode of the TFT. The sidewall spacer electrode regions are connected to the horizontal regions of the third polysilicon. Thus the top and bottom electrode are also electrically connected together. The source and drain regions are doped selectively. By choice of implant conditions, the off-set region having a desired dopant concentration different from the device layer concentration, can be formed at the drain side of the dual gated TFT.
REFERENCES:
patent: 4924279 (1990-05-01), Shimbe
patent: 5001540 (1991-03-01), Ishihara
patent: 5108938 (1992-04-01), Solomon
patent: 5160491 (1992-11-01), Mori
T. Hashimoto, et al., "Thin Film Effects of Double-Gate Polysilicon MOSFET" Extended Abstracts of the 22nd (1990 International) Conference on Solid State Devices and Materials, Scandai, pp. 393-396, 1990.
K. Itahashi, et al., "A Split Wordline Cell for 16Mb SRAM Using Polysilicon Sidewall Contacts" IEEE. IEDM 91-477, pp. 17.4.1-17.4.4, 1991.
C. T. Liu, et al., "High Reliability and High Performance 0.35um Gate Inverted TFT's for 16Mbit SRAM Applications Using Self-Aligned LDD Structures" AT&T Bell Labs, IEEE, IEDM 92-823, pp. 32.7.1-32.7.4, 1992.
International Business Machines - Corporation
Srikrishnan Kris V.
Wojciechowicz Edward
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