Vertical-conduction and planar-structure MOS device with a...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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Details

C257S256000, C257S263000, C257SE29265, C257SE29059

Reexamination Certificate

active

11279967

ABSTRACT:
A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

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patent: 5939752 (1999-08-01), Williams
patent: 6040598 (2000-03-01), Nakayama et al.
patent: 6225669 (2001-05-01), Long et al.
patent: 2003/0057478 (2003-03-01), Yun et al.
patent: 0119400 (1984-09-01), None
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patent: 0 747 968 (1996-12-01), None
patent: 01005070 (1989-01-01), None

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