Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With extended latchup current level
Reexamination Certificate
2001-05-15
2003-08-26
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
With extended latchup current level
C257S170000, C257S109000
Reexamination Certificate
active
06611006
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power components and more specifically to an optimization of the breakdown voltage of vertical type power components, the rear surface of which is capable of being soldered to a heat sink.
2. Discussion of the Related Art
FIG. 1
very schematically shows a partial cross-section view of a portion of a conventional high-voltage power component in a border region thereof. The component, a portion only of which is illustrated, is formed in a lightly-doped silicon substrate
1
. In the present description, it will be considered that this substrate is of type N but, of course, all conductivity types may be inverted. The component is delimited at its periphery by a P-type isolating wall
2
extending from the upper surface to the lower surface of the substrate.
In a current configuration of high-voltage vertical semiconductor components, a P-type layer
3
is formed, continuously or not, on the lower substrate surface and extends to reach the isolating wall. On the upper substrate surface side, a layer
4
, also of type P, is present. P-type layer
4
, N-type substrate
1
, and P-type layer
3
are layers that constitute a high-voltage vertical component, the high breakdown voltage being especially due to the large thickness and to the low doping level of substrate
1
. PNP layers
4
-
1
-
3
may, for example, form a transistor.
A rear surface metallization M
1
is in contact with the entire rear surface of the component and a metallization M
2
is connected, directly or indirectly, to layer
4
. This connection is direct in the case where a PNP transistor is desired to be formed. In the shown case, where it is desired to form a thyristor with or without a gate, an additional heavily-doped N-type layer
5
is formed to form the cathode of the thyristor in contact with metallization M
2
. The periphery of layer
4
is spaced apart from isolating wall
2
by a portion of substrate
1
and preferably includes a lightly-doped P-type area
6
(P−) deeper than region
4
.
When a positive voltage is applied between metallizations M
1
and M
2
, the blocking (non-conducting) junction is the junction between substrate
1
and P region
4
-
6
. Around this junction, the breakdown voltage is determined by a so-called space charge area delimited by equipotential surfaces E
1
L and E
1
H, shown in dotted lines in the drawing. Equipotential surface E
1
L indicates the area at the low potential of electrode M
2
, for example, 0 volts. Equipotential surface E
1
H designates the area at the high potential of electrode M
1
, for example, 600 volts.
When the device is reverse biased, that is, when metallization M
2
is positively biased with respect to metallization m
1
, the breakdown voltage is essentially provided by the junction between substrate
1
, and on the one hand P layer
3
, on the other hand isolating wall
2
. The limits of the space charge area, that is, the equipotential surfaces at the low potential and at the high potential, respectively, have been designated by E
2
L and E
2
H. For a device to have a high breakdown voltage, the extreme equipotential surfaces must be as spaced apart as possible to avoid reaching the breakdown voltage in the semiconductor (on the order of 20 V/&mgr;m). Thus, one of the layers in the vicinity of the junction providing the breakdown voltage must have relatively light doping so that the space charge area can extend widely enough therein.
Independently from the need to provide a sufficient breakdown voltage of the component when high voltages are applied thereacross, leakage current problems are also posed. For various reasons, for example due to contamination of the oxides, the N substrate
1
may be strongly depleted at the surface under an upper insulator layer
7
. A population inversion may even be achieved in this surface region. There then appears a channel region ensuring an electric continuity between the external periphery of P region
6
and the internal periphery of isolating wall
2
. To avoid such leakage currents, it is known to use a so-called stop-channel region formed of a heavily-doped N-type (N+) region
8
at the surface of substrate
1
between the external periphery of region
6
and the internal periphery of wall
2
. Although this is not shown in the cross-section view, area
8
forms a ring that extends over the entire periphery of the involved component. Given its high doping level, N+ ring
8
is not likely to be inverted and thus interrupts any inversion channel that could form at the component surface. To favor the equipotentiality of stop-channel ring
8
and avoid a localized depletion, it is conventional to coat diffused ring
8
with a metallization (not shown). To favor the spreading of the equipotential surfaces, in reverse biasing, it is also known to coat the upper surface of isolating wall
2
with a metallization
9
that partially extends towards the inside above insulator
7
, thus forming a field plate.
Thus, with peripheral structures of the type of that in
FIG. 1
in which the component is surrounded with an isolating wall, very good breakdown voltage properties are obtained. However, this requires very long diffusions at high temperatures, for example 300 hours at 1280° C. Further, these diffusions, once performed, occupy a non-negligible surface that may even be greater than the surface of the component that they delimit.
It has thus been attempted to form peripheral structures with no isolating wall. An example of such a structure is illustrated in FIG.
2
A. On the upper surface side, substantially the same elements as in
FIG. 1
are shown, except for the fact that there is no lateral P well. An N+-type region
10
is only formed at the vicinity of the periphery. Region
10
will preferably be more distant from the outer edge of P-type region
6
than was stop-channel region
8
of FIG.
1
.
On the lower surface side, a structure substantially symmetrical to that of the upper surface is formed. Thus, P-type region
3
is interrupted and is surrounded with a lightly-doped P-type region
12
similar to region
6
on the upper surface side. Also, on the lower surface side, an isolating layer
13
is deposited at the component periphery and metallization M
1
is in contact with the sole P+ region and extends slightly above isolating region
12
. An N+-type region
14
is also formed at the component periphery.
This type of structure, in addition to the fact that it poses more delicate breakdown voltage problems than in the case of
FIG. 1
, poses a problem when forming the solderings. Conventionally, a vertical component is entirely soldered by its lower surface on a radiator or heat sink via a land for soldering
20
(FIG.
2
B). If the heat sink extends over a surface at least equal to the lower surface of the component, soldering
20
tends to have a greater lateral extension and possibly to continue upwards along the component surface. This upward extension is designated by reference
22
. This structure has a double disadvantage. On the one hand, the soldering has a field plate function and tends to have potential E
2
H extend to N+ region
14
and alter the breakdown voltage. On the other hand, soldering extension
22
forms a short-circuit for the component.
To avoid these problems, a heat sink such as illustrated in
FIG. 2C
, having an upper surface including a boss
24
of smaller surface area than the land intended to be assembled thereon, tends to be used. Thus, soldering
20
, even if it exhibits a slight extension
26
, will not act as a field plate tending to spread equipotential surface E
2
H and will not tend to create a short-circuit either. This solution provides satisfactory results but poses manufacturing problems. Indeed, the size of boss
24
is linked to the chip size. A specific heat sink must thus be provided for each chip dimension, not to mention positioning difficulties.
Another solution also provided to solve this type of problem is to dig into the component
Anastasi John N.
Dickey Thomas L.
Morris James H.
STMicroelectronics S.A.
Tran Minh Loan
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