Vertical chip mount memory package and method

Details Vertical chip mount memory package and method Vertical chip mount memory package and method

1993-11-02

1995-03-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437211, 437214, 437217, 437220, H01L 2160

Patent

active

053977475

ABSTRACT:
A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19) mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form memory chip cube. One is a high melting point lead tin alloy (HMA), the other is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over another functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs. The memory cube (42) is formed by joining the memory chip pairs together in a boat (30) with a silicon bar (41) maintaining spacing during manufacture. The memory chip cube (42) as well as the supporting chips are then placed and joined to the packaging substrate. The supporting silicon bar is removed from the memory chip cube (42) by re-heating the cube after it is joined to the packaging substrate. The package is completed by following with capping of the chip package of the paired memory chip cube with its attached packaging substrate by attaching to the base member substrate an appropriate heat sink after appropriate I/O flex lines are in place.

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Henle, "Verticle Chip Packaging", IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978.

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