Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Plural non-isolated transistor structures in same structure
Reexamination Certificate
2003-02-28
2004-11-09
Brewster, William M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
Plural non-isolated transistor structures in same structure
C257S585000, C257S593000, C438S313000, C438S339000, C438S345000, C438S353000, C438S357000
Reexamination Certificate
active
06815801
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor device and, more specifically, to a vertical bipolar transistor, a method of manufacture thereof, and an integrated circuit including the same.
BACKGROUND OF THE INVENTION
The advent of the integrated circuit has had a significant impact on various types of communication devices. For example, the integrated circuit has been incorporated into both radio frequency applications and high speed communication network systems, as well as many other systems. While the reliability and operation speeds of these communication devices have dramatically increased, those skilled in the art still pay a substantial amount of attention to optimizing such properties.
One device that has garnered specific attention of late, is that of the bipolar transistor, and particularly, the PNP-type bipolar transistor. As those skilled in the art are well aware, PNP-type bipolar transistors have a number of uses. Lately, however, PNP-type bipolar transistors have found substantial use as the output (pass) device in many low dropout regulators. Often, such low dropout regulators are useful in battery applications, such as cell phones.
Initially, lateral PNP-type bipolar transistors were chosen for use as the output (pass) devices. This decision was made at least in part because the manufacture of the lateral PNP-type bipolar transistors fits extremely well into the “typical” standard bipolar transistor process flow. Accordingly, the lateral PNP-type bipolar transistors are easily integrated with various NPN-type bipolar transistors, as well as conventional CMOS transistors.
Unfortunately, however, the lateral PNP-type bipolar transistor suffers from poor packing density, its beta peaking at a low current density due to its base being comprised of an N-type epitaxial (EPI) layer, and poor AC performance due to the typically large base-width requirements. Nonetheless, it is desirable to have a device whose electrical characteristics (magnitude and current density of the peak beta) are not coupled to the N-type EPI layer doping, and whose AC characteristics are not a function of the lithography used in a 2 &mgr;m “standard” bipolar process flow. The lateral PNP-type bipolar transistors, however, are not sufficiently capable of consistently providing such properties.
As a result, the industry has recently turned to vertical PNP-type bipolar transistors for use as the output (pass) devices. While the vertical PNP-type bipolar transistors do not normally experience the aforementioned drawbacks of the lateral PNP-type bipolar transistors, their use generally requires a trade-off in the performance of any NPN-type bipolar transistors located proximate thereto. Furthermore the vertical PNP-type bipolar transistors typically involve exotic diffusion cycles or EPI recipes, using a combination of both P and N-type EPI materials. Any flow which requires both types of EPI would similarly require two sets of EPI equipment and therefore is generally undesirable.
Additionally, problems exist with isolating the collector of the vertical PNP-type bipolar transistors, as well as reducing the collector resistance to as low a value as possible. In many conventional vertical PNP-type bipolar transistor flows, the collector of the device is not truly isolated from the substrate. This often makes the vertical PNP-type bipolar transistor unsuitable for certain applications.
The industry has attempted to correct the aforementioned collector isolation problem. For example, in certain cases where collector isolation is achieved, much of the previous work has been to place an N- diffusion into the starting substrate, drive it in, and then place the buried portion of the vertical PNP-type bipolar transistor's collector (P-type buried collector) directly into this N-type region.
Unfortunately, this process has at least two drawbacks. First, the breakdown voltage of the transistor is greatly reduced because two highly doped junctions are placed together. Second, the N-type diffusion “pinches” the P-type buried collector making it more resistive, and thus reducing its capacities at high current levels. This type of device will normally saturate at relatively low current densities, which as those skilled in the art well understand, is undesirable.
To overcome the aforementioned “pinching” effect, the industry has attempted to increase the doping of the P-type buried collector to a very high level. This has the disadvantage that during subsequent EPI growth cycles the out-gassing and updiffusion of the P-type collector is greatly increased, causing the collector to be shorted to the isolation. In effect, this substantially defeats the purpose of the N-type isolation diffusion.
To overcome the “out-gassing” from the highly doped P-type collector, an N+ “spacing” diffusion may be placed between the vertical PNP-type bipolar transistor's subcollector and the adjacent isolation. A drawback of this approach is that it reduces the operating voltage of the device, increases the size of the transistor, and in some cases requires an additional mask/implant step. Other solutions require the addition of large numbers of “spacing” diffusions to ensure isolation. These, however, also have the effect of growing the size of the transistor.
Accordingly, what is needed in the art is a vertical PNP-type bipolar transistor that does not experience the problems associated with conventional vertical PNP-type bipolar transistors, however, one that can also be easily incorporated into the “typical” standard bipolar transistor process flow.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a vertical bipolar transistor, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor may include, in one embodiment, a second epitaxial layer located over a first epitaxial layer, wherein the second epitaxial layer includes at least two dopant profiles. The vertical bipolar transistor may further include a collector, a base and an emitter located over or within the second epitaxial layer.
The present invention further includes a method for manufacturing the vertical bipolar transistor disclosed above, as well as an integrated circuit including the vertical bipolar transistor. The integrated circuit, in addition to that disclosed above, may further include an NPN transistor located above the second epitaxial layer and proximate the vertical bipolar transistor, as well as interconnects contacting the vertical bipolar transistor and NPN bipolar transistor to form an operative integrated circuit.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.
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patent: 2003/0219952 (20
Govindaraju Venkatesh
Jasper Scott F.
Lisenby James
Najfus Philip
Oglesby, Jr. Darrel C.
Brady III W. James
Brewster William M.
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instrument Incorporated
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