Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-01-06
2002-07-16
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000
Reexamination Certificate
active
06420782
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of integrated circuit packaging, and more specifically, can relate to an apparatus and method for creating substantially vertically mountable integrated circuit packages that can be electrically connected to a circuit board by a lateral ball grid array.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described connection with memory modules, as an example.
Heretofore, in this field, integrated circuits have been formed on semiconductor wafers. The wafers are separated into individual chips and the individual chips are then handled and packaged. The packaging process is one of the most critical steps in the integrated circuit fabrication process, both from the point of view of cost and of reliability. Specifically, the packaging cost can easily exceed the cost of the integrated circuit chip and the majority of device failures are generally packaging related.
The integrated circuit must be packaged in a suitable medium that will protect it in subsequent manufacturing steps and from the environment of its intended application. Wire bonding and encapsulation are the two main steps in the packaging process. Wire bonding connects the leads from the chip to the terminals of the package. The terminals allow the integrated circuit package to be connected to other components. Following wire bonding, encapsulation is employed to seal the surfaces from moisture and contamination and to protect the wire bonding and other components from corrosion and mechanical shock.
Conventionally, the packaging of integrated circuits has involved attaching an individual chip to a lead frame, where, following wire bonding and encapsulation designated parts of the lead frame become the terminals of the package. The, packaging of integrated circuits has also involved the placement of chips on a surface where, following adhesion of the chip to the surface and wire bonding, an encapsulant is placed over the chip to seal and protect the chip and other components.
SUMMARY OF THE INVENTION
Commonly, integrated circuit packages are attached to other components to form a module. Memory chip packages, e.g., are mounted on a board to form a single inline memory module (SIMM). SIMMs may, for example, be used to increase the memory of typically personal computers. As memory demands increase, so has the need for increased Input/Output (I/O) capacity and memory capacity of memory module. Efforts to enhance these capacities, however, have been limited by the amount of surface space available on the SIMM surface. Space may also be limited in the environment in which SIMMs operate. Furthermore, the surface area occupied by the individual memory units limits both the distance between connection, but also, the number of memory units that may be positioned on a single mother or sister-board.
Therefore, it is recognized herein that a need has arisen for increasing the density of memory and other semiconductor circuits on each mother or sister-board and that a need has also arisen for a process for producing high density arrangements that provide for the close proximity of integrated circuit packages to reduce interconnect distance, and that a need has arisen for materials and methods that lead to increases in I/O and/or memory capacity. Further, a need has arisen for an integrated circuit package that provides protection to the wire bonding and silicon chip during subsequent manufacturing and testing steps and from the environment of its intended purpose.
The present invention disclosed herein includes a high density integrated circuit module and a process for producing such a module that provides for vertical alignment of integrated circuit packages. The packaging also protects the components of the integrated circuit package during manufacturing and testing steps and from the environment of its intended purpose. The individual integrated circuit packages can be angle-mounted on a circuit board, with the packages adjacent (e.g., parallel) to each other and attached to either or both sides of the circuit board to form a module.
The invention can include an integrated circuit package comprising a carrier having a top surface and a terminal mounted flat on the surface of a side. The side and the side surface terminal are generally at an angle to the top surface. In one embodiment the side surface is generally perpendicular to the top surface. The side, however, can be at an angle from 30 to 90 degrees (but preferably at least 45) relative to the top surface.
The carrier can be a circuit board type of material, such as a high temperature epoxy resin, and has one or more routing strips that are integral to the carrier. Integral to the carrier means that the routing strips can be within or on the surfaces of the carrier. One or more terminals are disposed on a side surface of the carrier, with at least one of the pads being electrically connected with at least one of the routing strips. A chip, such as a silicon chip, is adhered to the carrier, the chip having one or more bonding pads. Wire bonding may electrically connect the one or more bonding pads to at least one of the routing strips and potting material may fill the opening within the carrier to cover the wire bonding and the bonding pads.
In one embodiment of the present invention the integrated circuit package further. comprises at least one solder ball disposed on at least one of the side surface terminals disposed on the carrier. The carrier and the package have a common side, and the side surface terminals are on this common side. Thus, the terminals are on the side of both the carrier and the package. Potting material may also encapsulate the chip and have a thickness of, for example, about 6 mils. The carrier for use with this embodiment will typically have a thickness of at least about 10 mils, depending on the size of the solder ball connection. In one embodiment of the present invention the overall thickness or profile of the package is between about 40 mils and 50 mils. In yet other embodiments the thickness of the package is about 41, 44, 47 or 50 mils.
Yet another embodiment of the present invention is a high density memory module comprising a horizontal circuit board and at least one vertical integrated circuit package having side-mounted bonding pads electrically connected to the circuit board. The high density module may further comprise a plurality of tabs being integral with the top or the bottom of the circuit board. The high density module may further comprise solder balls disposed between the integrated circuit package and the carrier.
Yet another embodiment of the present invention is a high density module produced by a process comprising the steps of, obtaining a circuit board having a top and a bottom and electrically connecting at least one vertical integrated circuit package to the top of the circuit board. The process may further including the step of electrically and perpendicularly connecting at least one integrated circuit package to the bottom of the circuit board. The present invention may also include the step of disposing at least one solder ball between at least one terminal of the integrated circuit package and at least one tab on the top of the circuit board. Alternatively, solder columns may be disposed is between the integrated circuit module and the first side of the carrier.
In one embodiment, the chip is adhered to a carrier and has bonding pads disposed thereon. Wire bonding electrically connects the bonding pads to the routing strips. A potting material in the opening provides protection to the wire bonding.
The integrated circuit package can further include bus bars being integral with the carriers and extending into the openings. The bus bar electrically connects at least one of the bonding pads of the chip to at least one the terminals disposed on the first and the second surfaces of the carrier.
The integrated circuit module is formed by electrically connecting at least one or the side surface termi
Eng Kian Teng
Yeow Lee Teck
Brady III Wade James
Potter Roy
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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