Vertical and lateral isolation for a semiconductor device

Details Vertical and lateral isolation for a semiconductor device Vertical and lateral isolation for a semiconductor device

1994-07-06

1995-08-22

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257522, 257509, 257502, H01L 2704, H01L 2712

Patent

active

054442893

ABSTRACT:
A method is provided for making a power device (54) and a small signal device (52) on a bonded silicon substrate (41). A first silicon substrate (10) provided. A first surface (17) is etched to form a plurality of cavities (11) with a depth (13). A dielectric layer (14) is created on the first surface (17), wherein the dielectric layer (14) is created with a thickness less than or equal to the depth of the plurality of cavities. The dielectric layer (14) is patterned so that a plurality of islands (22) of dielectric remain in the cavities. A second silicon substrate (42) is provided. The first and the second silicon substrates (10, 42) are bonded together in such a manner that the islands (22) are buried. A predetermined portion of the first silicon substrate (10) is removed, thereby creating a surface that is suitable for semiconductor device fabrication.

REFERENCES:
patent: 4638552 (1987-01-01), Shimbo et al.
patent: 4710794 (1987-12-01), Koshino et al.
patent: 5072287 (1991-12-01), Nakagawa et al.
patent: 5204282 (1990-04-01), Tsuruta et al.
Haisma et al. "Silicon-on--Insulator Wafer Bonding-Wafer Thinning Technological Evaluations" Jap. Journ. of Appl. Physics vol. 28, No. 8, 1989 pp. 1426-1443.

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