Vertical and lateral insulated-gate, field-effect transistors, s

Details Vertical and lateral insulated-gate, field-effect transistors, s Vertical and lateral insulated-gate, field-effect transistors, s

1992-09-28

1993-12-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 48, 437 6, 437154, 437158, 148DIG126, H01L 21265

Patent

active

052720985

ABSTRACT:
A field effect transistor (147) is formed in a region of a second semiconductor layer (171), having a first conductivity type. A tank region (196) of a second conductivity type opposite the first conductivity type is formed in the semiconductor region (171), and defines a tank area on the face of the semiconductor layer (171). A first highly doped region (276) formed to be of the first conductivity type is formed within the region (171) and to be spaced from the tank region (196). A gate insulator layer (218) is formed on at least one selected portion of the face, this selected portion including a portion of the tank area (196). A conductive gate (246) is formed on the gate insulator layer over the selected portion of the face. At least one second highly doped region (278) is formed at the face within the tank area to be of the first conductivity type, and to have at least one lateral edge self-aligned to a corresponding one of the lateral edges of the gate (246 ). The tank area forms a channel between the first highly doped region (276) and the second highly doped region (278).

REFERENCES:
patent: 4569117 (1986-02-01), Baglee et al.
patent: 4639754 (1987-01-01), Wheatley, Jr. et al.
patent: 4669177 (1987-06-01), D'Arrigo et al.
patent: 4695979 (1987-02-01), Tuvell et al.
patent: 4715014 (1987-12-01), Tuvell et al.
patent: 4718041 (1988-01-01), Baglee et al.
patent: 4736342 (1988-05-01), Imondi et al.
patent: 4742492 (1988-05-01), Smayling et al.
patent: 4797372 (1989-01-01), Verret et al.
patent: 4804637 (1989-02-01), Smayling et al.
patent: 4879254 (1989-11-01), Tsuzuki et al.
patent: 4887142 (1989-12-01), Bertotti et al.
patent: 4912676 (1990-03-01), Patterson et al.
patent: 4914047 (1990-04-01), Seki
patent: 4914051 (1990-04-01), Huie et al.
Surinder Krishna, et al., "An Analog Technology Integrates Bipolar, CMOS and High-Voltage DMOS Transistors", IEEE, 1984, pp. 89-95.
Zahir Parpia, et al., "Modeling and Characterization of CMOS-Compatible High-Voltage Device Structures": IEEE, 1987, pp. 2335-2343.
Dumitru Cioaca et al., "A Million-Cycle CMOS 256K EEPROM", IEEE, 1987, pp. 684-691.
K. Y. Chang et al., "An Advanced High Voltage CMOS Process for Custom Logic Circuits with Embedded EEPROM", IEEE, 1988 Custom Integrated Circuits Conference, 25.5.1-25.5.5.

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