Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2006-06-13
2006-06-13
Nguyen, Cuong (Department: 2811)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S133000
Reexamination Certificate
active
07060538
ABSTRACT:
The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The system includes the silicon controlled rectifier, which has a first p-type region (508) coupled to a voltage node (504), a first n-type region (512) having a first side adjoining the first p-type region, a second p-type region (510) having a first side adjoining a second side of the first n-type region, and a second n-type region (514) having a first side adjoining a second side of the second p-type region. A clamping structure (506) is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure (518) is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.
REFERENCES:
patent: 6671153 (2003-12-01), Ker et al.
Brady III W. James
Keagy Rose Alyssa
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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