Versatile reconfigurable matrix based built-in self-test process

Details Versatile reconfigurable matrix based built-in self-test process Versatile reconfigurable matrix based built-in self-test process

1993-09-24

1996-01-16

Voeltz, Emanuel T.

Excavating

371 223, G06F 11267, G06F 1127, G01R 313185, G01R 313187

Patent

active

054854679

ABSTRACT:
A built-in self-test circuitry includes a design under test and a self-test processor. Included within the design under test is a plurality of scan row registers. The self-test processor includes a command processing section and a signal generating section. The command processing section receives information which indicates the configuration of the scan row registers. The signal generating section generates control signals which control the built-in self-testing of the circuit. The control signals are based on the information received by the command processing section. In the preferred embodiment, the command processing section includes a shift section, a load section, and a signature section. The shift section receives information which indicates a number of bits in each scan row register. The load section receives information which indicates a number of loads into the scan row registers. The signature section receives information which indicates a bit length of signature registers used to generate a checksum. The signature section additionally receives information which indicates a number of scan row registers.

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M. Nicolaidis, et al. Silicon Compilation of Hierarchical Control Sections With Unified BIST Testability, Microprocessors, vol. 15, No. 5, Jun. 1991, London GB, pp. 257-269.

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