Versatile memory controller chip for concurrent input/output ope

Details Versatile memory controller chip for concurrent input/output ope Versatile memory controller chip for concurrent input/output ope

1990-11-28

1997-07-29

Swann, Tod R.

395872, 395858, G06F 1300

Patent

active

056529120

ABSTRACT:
A memory controller includes an input data path and an output data path. First circuitry generates signals to put the input data into at least one variably-dimensioned logical array of memory cells of a memory. Second circuitry generates signals to extract from the memory the contents of at least one variably-dimensioned logical array of memory cells. The memory may be double buffered such that data input to one of the portions may take place simultaneously as data output from the other of the portions. In a preferred embodiment, any combination of up to 254 total variable-dimensioned logical arrays of memory cells may be defined for input to and output from the memory. The memory controller may be viewed as supporting two simultaneous processes, an input "windowing" process for receiving windows of data and an output "windowing" process for simultaneously passing out windows of data. The memory controller is preferably realized in the form of a monolithic integrated circuit employing "bit-slice" architecture and is static and dynamic RAM-compatible.

REFERENCES:
patent: 4367466 (1983-01-01), Takeda et al.
patent: 4399435 (1983-08-01), Urabe
patent: 4442503 (1984-04-01), Schutt et al.
patent: 4511962 (1985-04-01), Machida et al.
patent: 4533910 (1985-08-01), Sukonick et al.
patent: 4546350 (1985-10-01), Tanaka
patent: 4573116 (1986-02-01), Ong
patent: 4642790 (1987-02-01), Minshull et al.
patent: 4649377 (1987-03-01), Urabe
patent: 4651146 (1987-03-01), Lucash et al.
patent: 4660155 (1987-04-01), Thaden et al.
patent: 4663735 (1987-05-01), Novak et al.
patent: 4694288 (1987-09-01), Harada
patent: 4843544 (1989-06-01), DuLac et al.
patent: 4885699 (1989-12-01), Taoda et al.
patent: 4961071 (1990-10-01), Krooss
patent: 4965748 (1990-10-01), Chang et al.
patent: 4985848 (1991-01-01), Pfeiffer et al.
patent: 5003471 (1991-03-01), Gibson
patent: 5014238 (1991-05-01), McLeish et al.

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