Vernier delay line interpolator and coarse counter realignment

Details Vernier delay line interpolator and coarse counter realignment Vernier delay line interpolator and coarse counter realignment

1997-03-11

1998-11-17

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Measuring or testing

368117, 368118, G06M 300

Patent

active

058387544

ABSTRACT:
A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.

REFERENCES:
patent: 4560939 (1985-12-01), DeKarske et al.
patent: 5062128 (1991-10-01), Katsuragi et al.
patent: 5703838 (1997-12-01), Gorbics et al.

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