Verifying configuration memory of a programmable logic device

Details Verifying configuration memory of a programmable logic device Verifying configuration memory of a programmable logic device

2011-03-22

2011-03-22

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S021000, C703S022000, C703S024000, C710S022000

Reexamination Certificate

active

07912693

ABSTRACT:
Systems and methods are provided for verifying respective configuration data values for programming configuration memory cells of an integrated circuit device such as a programmable logic device (PLD). Each configuration memory cell controls an input of a corresponding initialization value from a file in response to a selectable assertion of an initialization signal of a test bench during a logic simulation of the PLD. The file structurally associates the configuration memory cell with the corresponding initialization value. A current value of one or more of the configuration memory cells is written with the respective configuration data value via a configuration port of the PLD during the logic simulation. Each configuration memory cell compares its initialization and current values in response to a selectable assertion of a check signal of the test bench. A mismatch error is output in response to a difference between the initialization and current values of one or more of the configuration memory cells.

REFERENCES:
patent: 6389379 (2002-05-01), Lin et al.
patent: 6651225 (2003-11-01), Lin et al.
patent: 6810442 (2004-10-01), Lin et al.
patent: 7512850 (2009-03-01), Redgrave et al.
patent: 2002/0152060 (2002-10-01), Tseng
patent: 2003/0144828 (2003-07-01), Lin

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