Verifying circuit operation

Registers – Systems controlled by data bearing records – Time analysis

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G06F 1100

Patent

active

041846303

ABSTRACT:
A polynomial based apparatus, such as an error correcting apparatus, is checked by repeatedly supplying test bits to the apparatus. On even cycles, the modulo two sum of the signal contents should be zero, while on odd cycles it should be equal to the pattern used for test purposes.

REFERENCES:
patent: 3405258 (1968-10-01), Godoy et al.
patent: 3465132 (1969-09-01), Crockett et al.
patent: 3582633 (1971-06-01), Webb
patent: 3919533 (1975-11-01), Einolf, Jr. et al.
patent: 4048481 (1977-09-01), Bailey, Jr. et al.
patent: 4070565 (1978-01-01), Borrelli

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