Verifying an erase threshold in a memory device

Details Verifying an erase threshold in a memory device Verifying an erase threshold in a memory device

2011-06-07

2011-06-07

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090, C365S185110, C365S185290

Reexamination Certificate

active

07957198

ABSTRACT:
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).

REFERENCES:
patent: 6452840 (2002-09-01), Sunkavalli et al.
patent: 7283398 (2007-10-01), He et al.
patent: 7411824 (2008-08-01), Shibata et al.
patent: 2007/0014152 (2007-01-01), Shibata et al.
patent: 2007/0140015 (2007-06-01), Kawamura

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