1997-10-10
1999-11-23
Stamber, Eric W.
39550043, 39550006, G06F 1560
Patent
active
059915331
ABSTRACT:
A verification support system having the following characteristics: (1) Before actually making a CPU mounted circuit, virtually make a CPU mounted circuit model and an ICE model and perform verification of the CPU mounted circuit mode with logic simulation, by using the ICE model; (2) When an error is found in the verification of a program using logic simulation, the execution and verification of the steps up to one step before the error point is omitted and execution and verification are performed immediately from the error point, for the purpose of error correction; (3) A waveform obtained as a result of logic simulation and a partially enlarged waveform thereof are displayed on different display regions; (4) A display region for displaying a waveform obtained as a result of logic simulation every hour and a display region for saving a displayed waveform obtained when logic simulation is stopped, are provided separately; (5) When there are a plurality of target logic models, waveforms of logic simulation results are displayed on different display regions, respectively. The stop or restart of the renewing of waveforms can be performed individually or collectively; (6) Before making an actual system by PLC, virtually make a PLC model and a process model and verify the sequence program of the PLC; and (7) Prepare a test program for performing verification when a process model is detached from a PLC model, and verify a sequence program by using a general purpose simulator with a debugging function. The verification system enhances efficiency of development of a CPU mounted circuit, and development of a sequence control system using a PLC.
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patent: 5425036 (1995-06-01), Liu et al.
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Amano Yuji
Mizuta Yuko
Natsui Satoru
Noriyasu Manabu
Ogasawara Atsushi
Do Thuan
Kojima Moonray
Stamber Eric W.
Yokogawa Electric Corporation
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