Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2009-01-21
2011-11-22
Lin, Sun (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S106000, C716S113000, C716S132000, C716S133000
Reexamination Certificate
active
08065643
ABSTRACT:
An effective data amount and a power index of a module selected from a design target circuit are extracted from a time-series table database (DB) for each clock cycle. Time periods during which the effective data amount is “0” and there is a high possibility of improving power consumption, are identified. It is determined whether a first simulation result from the design target circuit and a second simulation result from the design target circuit into which a control circuit has been inserted to stop supplying a clock to the module continuously for the identified time periods coincide. Then, if the first simulation result and the second simulation result coincide, the time periods are determined as targets to which a clock gating is applicable.
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Fujitsu Limited
Greer Burns & Crain Ltd.
Lin Sun
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