Verification support apparatus, verification support method,...

Details Verification support apparatus, verification support method,... Verification support apparatus, verification support method,...

2009-01-14

2011-12-13

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S051000, C716S107000

Reexamination Certificate

active

08079003

ABSTRACT:
In a verification support apparatus, an implementation description of a verification target is acquired and based on the implementation description, a combination of input gates is identified. A pair of output cones including gates to which input signals from the input gates reach, and a common output cone including gates common to the pair of output cones, are detected. Based on the common output cone, a degree of relation between the input gates is calculated and according to the calculation, the strength of relation is determined for the combination of input gates. The strength of relation for a combination of the input gates is set, the combination being based on a specification of the verification target and corresponding to the combination identified from the implementation description. Whether the strength of relation set and that determined for the identified combination coincide is judged and a result of the judgment is output.

REFERENCES:
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patent: 7216318 (2007-05-01), Siarkowski
patent: A 7-35828 (1995-02-01), None
patent: A 7-49887 (1995-02-01), None
21. Saucier et el., “Partitioning with Cone Structures,” Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on, Nov. 7-11, 1993, pp. 236.

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