Verification of strongly ordered memory accesses in a functional

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395527, 364578, 3642643, G06F 1126

Patent

active

057940126

ABSTRACT:
A system and method for detecting architectural violations of strongly ordered instructions by a computer architecture under test that supports out-of-order instruction execution is presented. A synchronizer concurrently controls the execution of an architectural model, which models high-level architectural requirements of the computer architecture under test and generates correct results under all received instruction test stimuli, and a behavioral model, which models the high-level architectural requirements of the computer architecture under test and executes instruction test stimuli according to the out-f-order instruction execution behavior defined by the computer architecture. The synchronizer matches all out-of-order instruction execution effects. The synchronizer verifies the correct handling of strongly ordered instruction by the computer architecture under test by keeping track of coherency check addresses from the bus emulator to the behavioral model, each memory request issued by the behavioral model to the bus emulator for any memory address other than the coherency check address, each respective move-in of a copy of each memory address, each access of each of the logged memory addresses, and each access of each logged coherency check address. If between the issuance of a coherency check on a coherency check address and a subsequent access of the same coherency check address without a new move-in of the coherency check address, the behavioral model moves in a copy of a memory address and accesses that copy, an architectural violation in handling strongly ordered instructions by the computer architecture under test is indicated.

REFERENCES:
patent: 4890224 (1989-12-01), Fremont
patent: 5133058 (1992-07-01), Jensen
patent: 5357628 (1994-10-01), Yuen
patent: 5404496 (1995-04-01), Burroughs
patent: 5615357 (1997-03-01), Ball
patent: 5633812 (1997-05-01), Allen et al.
Thomas B. Alexander et al., "Verification, characterization, and debugging of the HP PA 7200 Processor", Hewlett-Packard Journal, pp. 34-43, Feb. 1996.
Doug Hunt, "Advanced performance features of the 64-bit PA-8000", IEEE, pp. 123-128, 1995.
Mark S. Papamaroose et al., "A low-overhead coherence solution for multiprocessors with private cache memories", IEEE, pp.348-354, 1984.
Thomas B. Alexander et al., "Verification, characterization, and debugging of the HP PA 7200 Processor", Hewlett-Packard Journal, pp. 34-43, 1996.
Doug Hunt, "Advanced performance features of the 64-bit PA-8000", IEEE, pp. 123-129, 1995.
Mark S. Papamaroose et al., "A low-overhead coherence solution for multiprocessors with private cache memories", IEEE, pp. 348-354, 1984.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Verification of strongly ordered memory accesses in a functional does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Verification of strongly ordered memory accesses in a functional, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Verification of strongly ordered memory accesses in a functional will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-400795

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.