Verification of spare latch placement in synthesized macros

Details Verification of spare latch placement in synthesized macros Verification of spare latch placement in synthesized macros

2011-06-28

2011-06-28

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Reexamination Certificate

active

07971162

ABSTRACT:
A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by said local clock buffer; measuring a distance between each of the local clock buffers without spare latches and a closest spare latch; running statistics for the local clock buffers from the measuring step; and locating macros with inadequate spare latch placement using the statistics.

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