Data processing: database and file management or data structures – Database design – Data structure types
Reexamination Certificate
1998-07-02
2001-05-22
Homere, Jean R. (Department: 2177)
Data processing: database and file management or data structures
Database design
Data structure types
36, 36, C707S793000
Reexamination Certificate
active
06237007
ABSTRACT:
TECHNICAL FIELD
The present invention relates to computer-aided design techniques and, more particularly, to the design of integrated circuitry using hardware description languages.
BACKGROUND INFORMATION
Hardware description languages, such as VHDL (Very High Speed Integrated Circuit Hardware Description Language), are widely used for the design, documentation, and simulation of integrated electronic circuitry. The 1993 version of VHDL is described in IEEE Standard VHDL Language Reference Manual, IEEE Std. 1076-1993. VHDL offers three different modes for the characterization of a complex integrated circuit: structural, data flow, and behavioral descriptions. The VHDL structural description mode focuses on the arrangement of interconnected hardware components, or “blocks,” defined by type and interface. The VHDL data flow description mode breaks down the circuit design into a set of register assignments that take place under the control of specified gating ports. The VHDL behavioral description mode defines the design in terms of a series of sequential modules that resemble a high-level programming language. A design can be characterized by a collection of structural, data flow, and behavioral descriptions.
In the VHDL structural description mode, the designer codes various component declarations that provide generic definitions of different hardware components such as multiplexers, latches, and shift registers. Once declared, a component can be instantiated as desired to define particular component instances, or “modules,” that form part of the overall integrated circuit design. A component declaration includes a component port list that defines the generic interface to the component, i.e., the input and output ports. A module declaration similarly includes a module port list, but specifies one or more particular signals to be connected to the port interface. Thus, a module, representing an instance of the component, assigns particular signals to the generic port list. In this manner, the module is interconnected with other modules in the overall design.
The human designer generally is required to manually enter the component port lists and module port lists. Unfortunately, the modules and associated port lists within a given design can be difficult to generate and maintain. As a design evolves, for example, the content of the port lists is subject to constant change. Moreover, the changes occur within an extremely complex design having potentially hundreds of modules and port lists that interact with one another. Consequently, maintenance of the module port lists presents a significant challenge.
If a port list is incorrect, the overall design or portions thereof may fail to simulate correctly. In particular, when the module port list omits one or more of the necessary ports, the associated module will not operate properly. Also, the port list error can propagate downstream to other modules that interface with the suspect module. Thus, lack of port list integrity compromises the function of the overall design and causes incorrect simulation.
Identification of the source of the problem, i.e., a defective port list, is a painstaking manual process that can take hours and, in many cases, days. This manual debugging effort can result in substantial delays and drains resources from the design effort, significantly increasing the design cycle and time to market. In the end, port list debugging is a costly nuisance that is difficult to avoid due to design complexity and the prevalence of human error.
SUMMARY
The present invention is directed to a method for analyzing the integrity of a port list for a component instance, or “module,” in a hardware description language file. The present invention also is directed to a computer readable medium encoded with a computer program arranged to execute such a method. An example of a hardware description language to which the method can be applied is VHDL.
The method compares a port list for a module that represents an instance of a component to an expected port list. The expected port list can be determined by reference to the port list of the particular component instantiated by the module. In the event the module port list deviates from the expected port list, e.g., the component port list, the integrity of the module port list can be compromised. In this case, an advisory can be generated to identify the deviation and, if desired, note its location within the hardware description language file. In this manner, the designer can quickly find a defective module port list and correct it prior to simulation.
A method configured according to the present invention can significantly reduce the time and effort involved in port list debugging. Consequently, the designer can devote more time and resources to the design effort and the end objective of producing the subject integrated circuit. In many cases, reduction of debugging costs will bear significantly on the final cost of the design. At the same time, reduction of debugging time can shorten the design cycle. Moreover, such a method can simply alleviate the considerable distraction and nuisance incurred by the designer as a result of port list errors.
The present invention, in one embodiment, provides a method for analyzing a port list in a hardware description language file, the hardware description language file declaring components and defining modules representing instantiated components, each of the modules being associated with one of the declared components, wherein each of the declared components includes a component port list and each of the modules includes a module port list, the method comprising accessing the hardware description language file, selecting one of the components from the hardware description language file, selecting one of the modules from the hardware description language file, wherein the selected module is associated with the selected component, extracting the component port list for the selected component, extracting the module port list for the selected module, comparing the extracted component port list and the extracted module port list, and generating an advisory in the event the extracted module port list deviates from the extracted component port list.
In another embodiment, the present invention provides a computer readable medium encoded with a computer program, the program being arranged such that, when the program is executed, a computer analyzes a port list in a hardware description language file, the hardware description language file declaring components and defining modules representing instantiated components, each of the modules being associated with one of the declared components, wherein each of the declared components includes a component port list and each of the modules includes a module port list, the computer performing the acts of accessing the hardware description language file, selecting one of the components from the hardware description language file, selecting one of the modules from the hardware description language file, wherein the selected module is associated with the selected component, extracting the component port list for the selected component, extracting the module port list for the selected module, comparing the extracted component port list and the extracted module port list, and generating an advisory in the event the extracted module port list deviates from the extracted component port list.
In a further embodiment, the present invention provides a method for analyzing a module port list in a hardware description language file, the module port list defining one or more ports for an instantiated component, the method comprising selecting a module port list from a hardware description language file, comparing the selected module port list to an expected port list, and generating an advisory in the event the selected module port list deviates from the expected port list.
In an added embodiment, the present invention provides a computer readable medium encoded with a computer program, the program being arranged such that,
Homere Jean R.
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
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