Verification environment creation infrastructure for...

Details Verification environment creation infrastructure for... Verification environment creation infrastructure for...

2008-01-01

2008-01-01

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S022000, C703S027000, C716S030000, C716S030000

Reexamination Certificate

active

11055275

ABSTRACT:
A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for the programmable logic device. The hardware specification can reference the bus functional model and at least one bus-based module interacting with the bus functional model. The verification environment for the programmable logic device can be automatically generated according to the interface description and the hardware specification.

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