Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
1998-10-22
2002-06-25
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S778000, C257S780000, C257S711000, C257S699000, C257S683000, C361S691000, C361S692000
Reexamination Certificate
active
06410981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packaged semiconductor device.
This application is based on patent application No. Hei 09-292941 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
In the past, in order to remove the moisture absorbed by a packaged semiconductor device comprising a process type electrode, such as a flip chip, a packaged semiconductor device comprising a vent formed at a cap, and a packaged semiconductor device comprising a vent formed at an isolated substrate have been suggested.
FIG. 6
shows one example of a packaged semiconductor device comprising a vent formed parallel to the direction of the thickness of the semiconductor chip at the isolated substrate.
In
FIG. 6
, reference symbols
1
to
9
respectively denote a cap
1
, a strengthening ring
2
, an isolated substrate
3
, a semiconductor chip
4
, a filler resin
5
, a BAG solder bump
6
, an adhesive
7
, a solder bump
8
, and a vent
9
.
As shown in
FIG. 6
, the moisture in the conventional packaged semiconductor device is generally discharged through the vents
9
formed at locations at which the semiconductor chip
4
is not positioned above the isolated substrate
3
.
In a second example of a packaged semiconductor device the moisture is discharged through a vent
10
formed parallel to the direction of the thickness of the semiconductor chip in the cap
1
of the packaged semiconductor device as shown in FIG.
7
. It is not necessary to form the vent
9
in the isolated substrate
3
as shown in
FIG. 7
; therefore, it is possible to increase the density of electrical wirings on the isolated substrate
3
, in response to the tendency of increasing pins.
When the packaged semiconductor device is loaded on the print substrate using a connecting material such as a conventional solder, the connection between the packaged semiconductor device and the print substrate is formed by heating the connecting material to higher than the melting temperature thereof using a reflowing oven, thereby the connecting material melts, cools and solidifies. The packaged semiconductor device is heated in this case; therefore, the moisture absorbed inside of the packaged semiconductor device vaporizes, or the air in the cavities formed inside of the packaged semiconductor device expands. Consequently, the pressure inside of the packaged semiconductor device is suddenly increased. Thus, the stress inside of the packaged semiconductor device is high, and the semiconductor package may crack; therefore, the reliability of the packaged semiconductor device is decreased. In order to maintain the reliability of the conventional packaged semiconductor device, the stress operating on the packaged semiconductor device is decreased by removing the moisture through the vents
9
and
10
shown in
FIGS. 6
or
7
.
The electrodes for connecting the semiconductor chip
4
and the isolated substrate
3
, and the electrical wirings are arranged on and around the isolated substrate
3
side by side in the conventional packaged semiconductor device. Therefore, when the vents
9
are to be formed at locations at which the semiconductor chip
4
is not positioned above the isolated substrate
3
, the problem arises that the greater the number of pins, the greater the difficulty in securing locations for the vents. Moreover, the diameter of the vents
9
is made small in order to secure locations for formation of the vents
9
, and the problem of increasing costs arises. Moreover, the BGA solder balls
6
for loading the packaged semiconductor device are put on the underside of the isolated substrate
3
; therefore, the vents
9
should be formed between these BGA solder balls
6
. Accordingly, when the packaged semiconductor device is loaded on a print board such as a mother board, flux and clearing solvent for the flux enter the vents
9
, as a result, permeability of the packaged semiconductor device becomes worse.
Because of these reasons, it gradually becomes difficult to form the vents
9
in the isolated substrate
3
.
In addition, formation of the vents
10
in the cap
1
as shown in
FIG. 7
has been suggested. When a heat sink is put on the cap
1
in order to improve heat loss properties, the problem arises that the vents
10
are covered with the heat sink; therefore the permeability of the packaged semiconductor device cannot be insured. Moreover, the heat generated in the packaged semiconductor device is removed by contacting the surface of the semiconductor chip to the cap
1
in a flip chip package. Therefore, when the vents
10
are formed in the cap
1
as shown in
FIG. 8
, the area for heat transfer is small. Consequently, the heat loss properties of the packaged semiconductor device become worse.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a packaged semiconductor device having high reliability which can solve the problems caused by the loading of a large number of pins, that is, the density of the electrical wirings becomes high, and the decreased heat loss properties thereof, and which can discharge the high pressure moisture in a gas state from the inside thereof to the exterior.
According to an aspect of the present invention, the present invention provides a packaged semiconductor device comprising:
a strengthening ring arranged around a semiconductor chip that includes a process type electrode and that is mounted on an isolated substrate;
a resin to fill spaces between the semiconductor chip and the isolated substrate; and
a cap arranged on the semiconductor chip and the strengthening ring,
wherein at least one vent is perpendicularly formed to the direction of the thickness of the semiconductor chip.
According to the packaged semiconductor device of the present invention, the permeability of the vents can be secured. Therefore, it is possible to remove the high pressure moisture in a gas state from the inside thereof to the exterior, and to prevent the occurrence of cracks therein. Consequently, the reliability of the packaged semiconductor device is improved.
Moreover, additional vents can be formed in the various isolated substrates, and caps.
However, it is not necessary to form the vents in the isolated substrates and the caps; therefore, the packaged semiconductor devices of the present invention can meet the tendency to increase the number of pins.
In particular, when the vents are formed at the boundary between the cap and the strengthening ring, or the boundary between the strengthening ring and the isolated substrate, a packaged semiconductor device having high reliability with low cost can be more easily obtained.
Moreover, when the strengthening ring is comprised of strengthening ring segments, the vents are formed at spaces between the strengthening ring segments, and the vents can be formed by arrangement of the strengthening ring segments. The packaged semiconductor device can be more easily obtained than the above packaged semiconductors of the present invention; and can decrease the cost.
According to another aspect of the present invention, the present invention provides a cap for a packaged semiconductor device, wherein vents are formed perpendicular to the direction of the thickness thereof.
According to another aspect of the present invention, the present invention provides a strengthening ring for a packaged semiconductor device, wherein vents are formed perpendicular to the direction of the thickness thereof.
REFERENCES:
patent: 5117281 (1992-05-01), Katsuraoka
patent: 5767568 (1998-06-01), Tsuruzono
patent: 5881944 (1999-03-01), Edwards et al.
patent: 5909057 (1999-06-01), McCormick et al.
patent: 5956576 (1999-09-01), Toy et al.
patent: 1132412 (1996-02-01), None
patent: 57-170554 (1981-04-01), None
patent: 403187247 (1991-08-01), None
patent: 5-166954 (1993-02-01), None
patent: 5-299536 (1993-11-01), None
patent: 6-132413 (1994-05-01), None
patent: 8-130268 (1996-05-01), None
Foley & Lardner
Loke Steven
Thai Luan
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