Vector selectable coordinate-addressable DRAM array

Details Vector selectable coordinate-addressable DRAM array Vector selectable coordinate-addressable DRAM array

1988-01-29

1991-01-08

Brier, Jeffery A.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340798, 364200, 3642551, 364900, 364955, G09G 102

Patent

active

049839586

ABSTRACT:
An improved memory organization system is described. The stored data is specially transformed so that a data bus can carry either a row or column vector of data equally well. The improved memory organization is contained in a computer system, where a computer processor is coupled to memory devices by a bus interface unit and a multiplex address bus to access vectors of data. The memory devices are enabled by the bus interface unit and a decoder which operate in combination to allow during each fetch that no more than one storage device per section of the data bus be enabled. Once a vector is fetched, it is sent through the data bus to the bus interface's barrel shifter where the data is properly transformed from its physical positioning to its logical positioning. The aligned vector is then sent to the computer processor. This invention is particularly well suited for manipulating pixel information. Slight variations on the present invention make it useful for both bit plane and packed pixel selectability. Other slight variations allow for arrays having three for more logical dimensions.

REFERENCES:
patent: 4038646 (1977-07-01), Mehta
patent: 4644503 (1987-02-01), Bantz et al.
patent: 4742474 (1988-05-01), Knierim
patent: 4745407 (1988-05-01), Costello
patent: 4766431 (1988-08-01), Kobayashi et al.
patent: 4773026 (1988-09-01), Takahara et al.
patent: 4845640 (1989-07-01), Ballard et al.

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