Vector scaling system for G.728 annex G

Details Vector scaling system for G.728 annex G Vector scaling system for G.728 annex G

2001-06-15

2004-12-21

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S208000

Reexamination Certificate

active

06834293

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to the field of information processing and more specifically to a vector scaling system for block floating point representation.
Conventional algorithms for vector scaling are well known. One such algorithm is the VSCALE routine defined by ITU (International Telecommunication Union)-T Recommendation G.728—Annex G. The recommendation relates to 16 kbit/s LD-CELP (code excited linear prediction) using a block floating point representation device. While directed to a 16-bit word size, it will be appreciated that VSCALE is applicable to other word sizes as well.
The importance of vector scaling for floating block representation cannot be over-emphasized. Vector scaling ensures the maximization of precision in fixed point DSP (digital signal processing) algorithms. Moreover, to obtain accuracy and consistency in fixed point fractional implementation, the vector values require left justification.
Generally, floating block representation is used for accommodating a more dynamic range of values (the ratio of the largest number represented to the smallest represented number that is non-zero for a given format). A floating point representation of a value comprises three portions, namely, a sign bit, an unsigned fractional number, and an exponent.
As shown,
FIG. 1
is a single precision, IEEE standard 754, single point precision floating point representation. In
FIG. 1
, the representation comprises a sign
102
bit for representing the sign of the entire number, an exponent
104
which is an 8-bit value representing the true exponent of the number V (see below) and offset by a predetermined bias, the bias being employed for comparing both positive and negative true exponents of floating point numbers; and a mantissa
106
which is a 23-bit number having a leading 1 bit (typically implied):
V
=(−1)
S
·2
E-bias
(1
·F
)
where S is the sign
102
bit,
E is the exponent
104
, and
F is the mantissa
106
.
This format can accommodate numbers having exponents from −127 to +128 in accordance with the IEEE standard 754. Various conventional techniques for scaling a vector are known.
One such scheme is the VSCALE originally proposed in G.728 Annex G. VSCALE is a pseudo-code for performing vector scaling for block floating point representation. Its purpose is to scale a vector of numbers so that the largest magnitude of its elements is left justified as desired. As discussed below, VSCALE initially conducts a maximum positive and negative value search of the vector elements. Thereafter, the result is classified into one of five cases. For each case, scaling is accomplished by looping and counting the number of shifts before a designated maximum or positive range. Disadvantageously, the VSCALE process results in relatively more complex code and relatively more time to accomplish scaling. For example, if a user wishes to scale a large vector, disadvantageously, additional time is needed by VSCALE to accomplish its objective.
Therefore, there is a need to resolve the aforementioned problems relating to the conventional approach for scaling vectors for floating point representation and the present invention and its embodiments meet this need.
BRIEF SUMMARY OF THE INVENTION
A first embodiment of the present invention is a system that reduces the complexity of the VSCALE routine in G.728 Annex G. This technique simplifies the maximum positive and negative value search in the vector and the calculation of the number of bit shifts needed for normalizing the vector by employing a pdmsb instruction. The pdmsb instruction is part of the SHx-DSP™ DSP instruction set, available from Hitachi, Inc., of Japan. The pdmsb instruction functions to find the number of bits to left-shift in order to left-justify a value.
According to another aspect of the present invention, a method for use in a fixed point arithmetic processing device having an input vector that contains one or more vector elements is disclosed. The input vector is an M bit integer, and a maximum permitted left shift (MLS) value for the input vector is less than or equal to the value of M−2. The method is for scaling all the vector elements based on the vector element with the largest magnitude. The method includes the following: sequentially searching each vector element to find a left shift value for scaling each vector element, and comparing the left shift values to determine a minimum left shift (NLS_MIN) for scaling the largest vector element.
Also, the method employs the NLS_MIN value to determine whether the input vector is a zero input vector, and if so, offsetting the NLS_MIN value by the MLS value to obtain an actual number of left shifts (NLS) value, for which the input vector would have been shifted but for the zero value. It is determined whether the input vector is a non-zero input vector, and if so, regardless of whether the largest magnitude element of the non-zero input vector has a positive or negative magnitude, offsetting the NLS_MIN value by the MLS value to obtain the NLS value for scaling the non-zero input vector.
According to another aspect of the present invention, the method further includes completing in one clock instruction the steps of sequentially searching, and comparing the left shift values with the pdmsb instruction. The pdmsb instruction finds the number of left shifts necessary to left justify a 2's complement 32-bit value in one instruction cycle.
According to another aspect of the present invention, a method, by a processing device, for scaling an M-bit integer input vector containing one or more vector elements. The method comprises receiving a maximum permitted shift (MLS) value for the input vector, said MLS value being less than or equal to M−2; determining a minimum left shift (NLS_MIN) for scaling said vector element with the largest magnitude; employing said NLS_MIN value to determine whether said input vector is a zero input vector, or a non-zero input vector irrespective of the positive or negative value of said largest element of non-zero input vector; if a zero input vector is determined, offsetting said NLS_MIN value by said MLS value to obtain an actual number of left shifts (NLS) value; determining whether said input vector is non-zero input vector, and if a non-zero input vector is determined, offsetting said NLS_MIN value by said MLS value to obtain said NLS value for scaling said non-zero input vector.
According to another aspect of the present invention, the step of offsetting said NLS_MIN value for said zero input vector further comprises said NLS value being given by: MLS+1.
According to another aspect of the present invention, offsetting said NLS_MIN value for said non-zero input vector further comprises said NLS value being given by: NLS_MIN+(MLS−(M−2)).
According to another aspect of the present invention, the method further comprises employing the pdmsb instruction for sequentially searching, and for comparing said left shift values.
According to another aspect of the present invention, employing said MLS_INPUT value further comprises determining whether NLS_MIN=31, if NLS_MIN≠31, then the input vector is a non-zero input vector.
According to another aspect of the present invention, a processor operable from an M-bit instruction set where M is an integer. The processor includes a memory unit for storing at least first instruction stream comprising M-bit instructions; an execution unit operable to receive execution signals to execute the M-bit instructions; a decode unit coupled to the memory unit and to the execution unit to receive and decode the first instruction stream from the memory unit to produce therefrom the execution signals.
The execution signals for: determining a minimum left shift (NLS_MIN) for scaling said vector element with the largest magnitude; employing said NLS_MIN value to determine whether said input vector is a zero input vector, or a non-zero input vector by evaluating if NLS_MIN=31; if NLS_MIN≠31, then the inpu

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