Boots – shoes – and leggings
Patent
1984-09-07
1988-08-02
Harkcom, Gary V.
Boots, shoes, and leggings
364200, G06F 700, G06F 900
Patent
active
047617543
ABSTRACT:
In a vector processor which is for use in combination with a main memory (11) and includes an input selecting arrangement (36), vector registers (21-28), a vector operation arrangement (31-34), and a store register (38). An output selecting circuit is not used on selecting operand vectors from vectors held in the vector registers. Instead, the vector registers are fixedly coupled to the vector operation arrangement to raise speed of operation and to simplify vector instructions. Preferably, vector memories are provided to retain vectors which need not be held in the vector registers and must have been stored in the main memory. In this event, a vector bypassing arrangement is used to bypass a result vector from the vector operation arrangement to one of the vector memories for storage therein as a bypassed vector. The input selecting arrangement is used on moving the bypassed vector to one of the vector registers.
REFERENCES:
patent: 4128880 (1978-12-01), Cray, Jr.
patent: 4302818 (1981-11-01), Niemann
patent: 4435765 (1984-03-01), Uchida et al.
patent: 4490786 (1984-12-01), Nakatani
patent: 4617625 (1986-10-01), Nagashima et al.
Harkcom Gary V.
NEC Corporation
Nguyen Long Thanh
LandOfFree
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