Vector processor performing data operations in one half of a tot

Details Vector processor performing data operations in one half of a tot Vector processor performing data operations in one half of a tot

1989-08-29

1992-05-19

Lee, Thomas C.

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3642318, 3642319, 36423221, 364247, 364243, 364270, 3642543, 364271, 36493151, 36496426, 36496429, 364934, 3649343, 364736, 364DIG1, 364DIG2, G06F 15347, G06F 1204, G06F 928, G06F 938

Patent

active

051153939

ABSTRACT:
Vector registers having logically equal address are arranged as two banks which can independently access ultra high speed RAM's. One bank holds all even-numbered elements of vector data and the other bank holds all odd-numbered elements of the vector data. A write address generator and a read address generator which are one half as fast as a clock rate of a machine cycle and which have a phase difference of one half period therebetween are provided so that the clock rate of the machine cycle may be set to one half of a total time of a write pitch and a read pitch of the vector registers.

REFERENCES:
patent: 4365294 (1982-12-01), Stokken
patent: 4573145 (1986-02-01), Ozawa
patent: 4661900 (1987-04-01), Chen et al.
patent: 4802131 (1989-01-01), Toyoda
patent: 4945479 (1990-07-01), Rusterholz et al.
patent: 4980817 (1990-12-01), Fossum et al.

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