Vector processing unit

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G06F 1516, G06F 15347

Patent

active

047915552

ABSTRACT:
A functional unit designed with arithmetic pipelining for vector processing is attached to a base data processor from which it receives vector instructions and operands for processing. Stepping of operands and exception indicators through the vector processing unit is controlled by the base processor. Exception information transferred to the base processor is controlled to provide precise indicators of error conditions for recovery and restart of vector processing. Masking logic provides for expansion/contraction of operands in the vector processing unit as compared with sequential main memory addresses.

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